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preliminary information AMD-756 peripheral bus controller data sheet publication # 22548 rev: b issue date: august 1999 tm
preliminary information trademarks amd, the amd logo, amd athlon, and combinations thereof, amd-750, amd-751, and AMD-756 are trademarks of advanced micro devices, inc. microsoft and windows are registered trademarks of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 1999 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth- erwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as com- ponents in systems intended for surgical implant into the body, or in other applica- tions intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to dis- continue or make changes to its products at any time without notice.
table of contents iii 22548b/0?august 1999 AMD-756? peripheral bus controller data sheet preliminary information contents 1 features 1 1.1 pci-to-isa bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 enhanced ide controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 universal serial bus controller . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 plug-n-play support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2overview 7 2.1 pci-to-isa bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 pci bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 pci bus target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 isa bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 eide controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 ordering information 15 4 signal descriptions 17 4.1 signal terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 a20m# (processor a20 mask) . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 cpurst# (processor reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.3 ferr# (floating point error) . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 ignne# (ignore numeric exception) . . . . . . . . . . . . . . . . . . 19 4.2.5 init# (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.6 intr (processor interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.7 nmi (non-maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . . 20
iv table of contents AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.2.8 smi# (system management interrupt) . . . . . . . . . . . . . . . . . 20 4.2.9 picclk (interrupt message bus clock) . . . . . . . . . . . . . . . . 20 4.2.10 picd0# and picd1# (interrupt message data bits) . . . . . . . 20 4.2.11 wsc# (write snoop complete) . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.12 stpclk# (stop clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.1 ad[31:0] (pci address/data bus) summary . . . . . . . . . . . . . 22 4.3.2 c/be[3:0]# ( pci command/byte enable) . . . . . . . . . . . . . . . . . 22 4.3.3 devsel# ( pci bus device select) . . . . . . . . . . . . . . . . . . . . . . 23 4.3.4 frame# ( pci bus cycle frame) . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.5 idsel (pci initialization device select) . . . . . . . . . . . . . . . . 24 4.3.6 irdy# ( pci bus initiator ready) . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.7 par (pci bus parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.8 pcirst# (pci reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.9 pclk (pci bus clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.10 pgnt# ( pci grant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.11 pirq[d:a]# ( pci interrupt requests) . . . . . . . . . . . . . . . . . . . 27 4.3.12 preq# ( pci request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.13 serr# ( system error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.14 stop# ( stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.15 trdy# (pci target ready) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 isa bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.1 aen (address enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.2 bale (bus address latch enable) . . . . . . . . . . . . . . . . . . . . . 29 4.4.3 bclk (bus clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4.4 dack[7:5]#, dack[3:0]# (dma acknowledge) . . . . . . . . . . 30 4.4.5 drq[7:5], drq[3:0] (dma request) . . . . . . . . . . . . . . . . . . . 30 4.4.6 iochck# (i/o channel check) . . . . . . . . . . . . . . . . . . . . . . . 30 4.4.7 iochrdy (i/o channel ready) . . . . . . . . . . . . . . . . . . . . . . . 31 4.4.8 iocs16# (16-bit i/o chip select) . . . . . . . . . . . . . . . . . . . . . . 31 4.4.9 ior# (i/o read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.10 iow# (i/o write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.11 irq15, irq14, irq[12:9], irq[7:3] (interrupt requests) . . 32 4.4.12 nmpirq (native mode primary ide port irq) . . . . . . . . . . 33 4.4.13 nmsirq (native mode secondary ide port irq) . . . . . . . . 33 4.4.14 la[23:17] (unlatched address) . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.15 master# (isa master cycle indicator) . . . . . . . . . . . . . . . . 33 4.4.16 memcs16# (16-bit memory chip select) . . . . . . . . . . . . . . . 34 4.4.17 memr# (memory read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.18 memw# (memory write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.19 osc (oscillator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.20 refresh# (refresh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.21 rom_kbcs# (rom and keyboard chip select) . . . . . . . . . 35 4.4.22 rstdrv (reset drive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
table of contents v 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.4.23 sa[16:0] (system address bus) . . . . . . . . . . . . . . . . . . . . . . . 36 4.4.24 sbhe# (system byte high enable) . . . . . . . . . . . . . . . . . . . . 36 4.4.25 sd[15:0] (isa system data) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4.26 smemr# (standard memory read) . . . . . . . . . . . . . . . . . . . . 36 4.4.27 smemw# (standard memory write) . . . . . . . . . . . . . . . . . . . 37 4.4.28 spkr (speaker) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.29 tc (terminal count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5 ultra dma enhanced ide interface . . . . . . . . . . . . . . . . . . . 38 4.5.1 daddrp[2:0] (primary ide address) . . . . . . . . . . . . . . . . . . 38 4.5.2 daddrs[2:0] (secondary ide address) . . . . . . . . . . . . . . . . 38 4.5.3 dcs1p# (primary port chip select) . . . . . . . . . . . . . . . . . . . . 38 4.5.4 dcs1s# (secondary port chip select) . . . . . . . . . . . . . . . . . . 39 4.5.5 dcs3p# (primary port chip select) . . . . . . . . . . . . . . . . . . . . 39 4.5.6 dcs3s# (secondary port chip select) . . . . . . . . . . . . . . . . . . 39 4.5.7 ddatap[15:0] (primary ide data bus) . . . . . . . . . . . . . . . . 39 4.5.8 ddatas[15:0] (secondary ide data bus) . . . . . . . . . . . . . . 40 4.5.9 ddackp# (primary ide dma acknowledge) . . . . . . . . . . . 40 4.5.10 ddacks# (secondary ide dma acknowledge) . . . . . . . . . 41 4.5.11 ddmardyp# (primary device dma ready, ultra dma mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5.12 ddmardys# (secondary device dma ready, ultradmamode) 41 4.5.13 ddrqp (primary ide dma request) . . . . . . . . . . . . . . . . . . 41 4.5.14 ddrqs (secondary ide dma request) . . . . . . . . . . . . . . . . 42 4.5.15 diorp# (primary i/o read) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.16 diors# (secondary i/o read) . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.17 diowp# (primary i/o write) . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.18 diows# (secondary i/o write) . . . . . . . . . . . . . . . . . . . . . . . 43 4.5.19 drdyp# (primary device ready) . . . . . . . . . . . . . . . . . . . . . 43 4.5.20 drdys# (secondary device ready) . . . . . . . . . . . . . . . . . . . 43 4.5.21 dstrobep (primary device strobe, ultra dma mode) . . . 44 4.5.22 dstrobes (secondary device strobe, ultra dma mode) . 44 4.5.23 hdmardyp# (primary host dma ready, ultra dma mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5.24 hdmardys# (secondary host dma ready, ultra dma mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5.25 hstrobep (primary host strobe, ultra dma mode) . . . . 45 4.5.26 hstrobes (secondary host strobe, ultra dma mode) . . 45 4.5.27 stopp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.28 stops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 system management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.1 c32khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.2 cache_zz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.3 pnpirq1 (plug and play interrupt request 1) . . . . . . . . . . 47
vi table of contents AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.6.4 cpusleep# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.5 pnpcs0# (plug and play chip select 0) . . . . . . . . . . . . . . . . 48 4.6.6 cpustop# (processor clock stop) . . . . . . . . . . . . . . . . . . . . 48 4.6.7 pnpcs1# (plug and play chip select 1) . . . . . . . . . . . . . . . . 48 4.6.8 dcstop# (dram controller stop) . . . . . . . . . . . . . . . . . . . . 48 4.6.9 pnpirq2 (plug and play interrupt request 2) . . . . . . . . . . 49 4.6.10 extsmi# (external smi input) . . . . . . . . . . . . . . . . . . . . . . . 49 4.6.11 bmreq# (pci bus master request) . . . . . . . . . . . . . . . . . . . 49 4.6.12 flagrd# (flag read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.6.13 pnpdak# (plug and play dma acknowledge) . . . . . . . . . . 50 4.6.14 flagwr (flag write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.6.15 pnpdrq (plug and play dma request) . . . . . . . . . . . . . . . . 50 4.6.16 intirq8# (internal real time clock interrupt) . . . . . . . . . 51 4.6.17 sqwave (square wave clock) . . . . . . . . . . . . . . . . . . . . . . . 51 4.6.18 pcistop# (pci bus clock stop) . . . . . . . . . . . . . . . . . . . . . . . 51 4.6.19 pnpirq0 (plug and play interrupt request 0) . . . . . . . . . . 51 4.6.20 pme# (power management interrupt) . . . . . . . . . . . . . . . . . 52 4.6.21 pwrbtn# (power button) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.6.22 pwrgd (power good) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.6.23 pwron# (main power on) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.24 ri# (ring indicator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.25 serirq (serial irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.26 msirq (mouse interrupt request) . . . . . . . . . . . . . . . . . . . . 53 4.6.27 smbalert# (smbus alert) . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6.28 smbusc (system management bus clock) . . . . . . . . . . . . . 54 4.6.29 smbusd (system management bus data) . . . . . . . . . . . . . . 54 4.6.30 slpbtn# (sleep button) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6.31 extirq8# (real time clock interrupt) . . . . . . . . . . . . . . . . 55 4.6.32 suspend# (processor suspend) . . . . . . . . . . . . . . . . . . . . . . 55 4.6.33 therm# (thermal warning detect) . . . . . . . . . . . . . . . . . . . 55 4.7 universal serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . 56 4.7.1 usbclk (universal serial bus clock) . . . . . . . . . . . . . . . . . . 56 4.7.2 usbp[3:0] (usb port [3:0] data positive) . . . . . . . . . . . . . . . 56 4.7.3 usbn[3:0] (usb port [3:0] data negative) . . . . . . . . . . . . . . 56 4.7.4 usboc0# (usb over-current detect 0) . . . . . . . . . . . . . . . . 56 4.7.5 usboc1# (usb over-current detect 1) . . . . . . . . . . . . . . . . 57 4.8 keyboard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.8.1 kbck (keyboard clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.8.2 ka20g (keyboard gate a20) . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.8.3 kbdt (keyboard data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.8.4 kbrc# (keyboard reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.8.5 keylock (keyboard lock) . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.8.6 dbrdy (debug ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.8.7 msck (mouse clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
table of contents vii 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.8.8 msdt (mouse data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.8.9 ekirq1 (external keyboard controller irq1) . . . . . . . . . . 59 4.8.10 ekirq12 (external keyboard controller irq12) . . . . . . . . 60 4.9 internal real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9.1 rtcx_in (crystal/oscillator input) . . . . . . . . . . . . . . . . . . . . 61 4.9.2 rtcx_out (crystal/oscillator output) . . . . . . . . . . . . . . . . 61 4.10 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10.1 gnd (power ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10.2 gnd_usb (usb differential output ground) . . . . . . . . . . . 62 4.10.3 v dd3 (power supply for the processor i/o voltage) . . . . . . . 62 4.10.4 v dd_ref (power reference) . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10.5 v dd_rtc (power supply to rtc) . . . . . . . . . . . . . . . . . . . . . . 62 4.10.6 v dd -soft (power supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10.7 v dd -usb (usb differential output power) . . . . . . . . . . . . . 62 5 functional operations 63 5.1 pci bus-initiated accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 pci bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.2 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.3 i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2.4 memory read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.5 configuration read and write . . . . . . . . . . . . . . . . . . . . . . . . 75 5.2.6 memory read multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.7 dual address line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.8 memory read line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.9 memory write invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 pci bus features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 back-to-back cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 subtractive decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.3 isa bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.4 isa bus-initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.1 dma-initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.2 isa bus master initiated cycles . . . . . . . . . . . . . . . . . . . . . . . 80
viii table of contents AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.5 pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.6 i/o and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.6.1 i/o mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.6.3 system rom memory mapping . . . . . . . . . . . . . . . . . . . . . . . 86 5.7 power planes and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.8 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.9 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.10 direct memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.10.1 dma controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.10.2 dma controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.10.3 middle address bit latches . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.10.4 page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.10.5 dma address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.10.6 type f dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.10.7 dma channel mapping registers . . . . . . . . . . . . . . . . . . . . . 98 5.10.8 ready control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.10.9 external cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.11 distributed dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.11.1 target dma channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.11.2 dma control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.11.3 dma software commands . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.11.4 dma addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.11.5 pci target dma configuration registers . . . . . . . . . . . . . . 105 5.12 isa bus refresh cycle types . . . . . . . . . . . . . . . . . . . . . . . . 105 5.13 fast ide/eide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.13.1 ide drive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.13.2 ide configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.13.3 ultra dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.14 power management support . . . . . . . . . . . . . . . . . . . . . . . . 111 5.14.1 power management subsystem . . . . . . . . . . . . . . . . . . . . . . 111 5.14.2 power plane management . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.14.3 sci and smi control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.14.4 system inactivity timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
table of contents ix 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.14.5 throttling logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.14.6 system power state controller (spsc) . . . . . . . . . . . . . . . . 118 5.14.7 serial irq protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.14.8 smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.14.9 plug and play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.14.10general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.14.11general-purpose i/o functions . . . . . . . . . . . . . . . . . . . . . . . 126 5.14.12amd-751? controller power management . . . . . . . . . . . . 128 5.14.13vdd_soft registers and logic . . . . . . . . . . . . . . . . . . . . . . 128 5.14.14rtc and cmos memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.15 universal serial bus controller (usbc) . . . . . . . . . . . . . . . 131 5.15.1 usbc miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . 134 5.15.2 system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.16 programmable interrupt controller (pic) . . . . . . . . . . . . . 141 5.16.1 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.17 i/o advanced programmable interrupt controller (ioapic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6 initialization 157 6.1 legacy i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.2 pci function 1 registers?ide controller . . . . . . . . . . . . . 164 6.3 pci function 3 registers?power management . . . . . . . . . 166 6.3.1 power management configuration space registers . . . . . 166 6.3.2 power management i/o space registers . . . . . . . . . . . . . . . 169 6.4 pci function 4 registers?usb controller . . . . . . . . . . . . 171 6.4.1 pins latched at the trailing edge of reset . . . . . . . . . . 172 7 registers 175 7.1 table conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.2 pci mechanism #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.3 register summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.4 legacy i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
x table of contents AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.4.1 keyboard controller registers . . . . . . . . . . . . . . . . . . . . . . . 187 7.4.2 dma controller i/o registers . . . . . . . . . . . . . . . . . . . . . . . . 192 7.4.3 interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . 194 7.4.4 interrupt controller shadow registers . . . . . . . . . . . . . . . . 195 7.4.5 timer/counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.4.6 cmos/rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.4.7 miscellaneous i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.5 function 0 registers (pci-isa bridge) . . . . . . . . . . . . . . . . 202 7.5.1 isa bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.5.2 distributed dma control . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 7.6 function 1 registers (enhanced ide controller) . . . . . . . 212 7.6.1 function 1 pci configuration space header . . . . . . . . . . . 213 7.6.2 ide configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 218 7.7 function 3 registers (power management) . . . . . . . . . . . . 223 7.7.1 function 3 pci configuration space header . . . . . . . . . . . 224 7.7.2 power management configuration registers . . . . . . . . . . . 225 7.7.3 power management i/o space registers . . . . . . . . . . . . . . . 242 7.7.4 processor power management registers . . . . . . . . . . . . . . . 247 7.8 function 4 registers (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . 270 7.8.1 function 4 usb configuration . . . . . . . . . . . . . . . . . . . . . . . 270 7.8.2 usb memory mapped registers (open hci registers) . . . 274 7.8.3 i/o apic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 8 electrical data 293 8.1 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 8.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 8.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 9 switching characteristics 299 9.1 osc switching characteristics . . . . . . . . . . . . . . . . . . . . . . . 300 9.2 pci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
table of contents xi 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.3 usb interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 9.4 isa interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 9.5 dma interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 9.6 eide interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 9.7 ultra dma-33 ide bus interface timing . . . . . . . . . . . . . . 325 10 pin designations 327 10.1 pin designation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10.1.1 state of pins at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 10.1.2 AMD-756 ? peripheral bus controller pin diagram . . . . . 335 10.1.3 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 11 package specifications 339
xii table of contents AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
list of figures xiii 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information list of figures figure 1. amd-750 ? chipset system block diagram . . . . . . . . . . . . . . . 2 figure 2. AMD-756 ? peripheral bus controller block diagram . . . . . . 8 figure 3. AMD-756 ? peripheral bus controller signal groups. . . . . . 14 figure 4. i/o access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 5. i/o cycle 16-bit to 8-bit conversion . . . . . . . . . . . . . . . . . . . . 66 figure 6. non-posted pci-to-isa access . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 7. posted pci-to-memory write . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 8. isa bus memory access cycle . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 9. isa bus memory cycle: 16-bit to 8-bit conversion . . . . . . . . 70 figure 10. memory cycle 32-bit to 8-bit conversion . . . . . . . . . . . . . . . . 71 figure 11. memory cycle 32-bit to 16-bit conversion . . . . . . . . . . . . . . . 72 figure 12. rom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 13. rom cycle 32-bit to 8-bit conversion . . . . . . . . . . . . . . . . . . 74 figure 14. configuration read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 15. configuration write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 16. subtractive decode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 17. dma transfer cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 18. isa bus master arbitration timing . . . . . . . . . . . . . . . . . . . . 81 figure 19. isa bus master-to-pci memory (memory read) . . . . . . . . . . 82 figure 20. isa bus master-to-pci memory (memory write). . . . . . . . . . 82 figure 21. normal power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 22. type f dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 23. dma ready timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 24. ide controller connections . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 25. power management and general purpose i/o . . . . . . . . . . . 111 figure 26. basic power management block diagram . . . . . . . . . . . . . . 112 figure 27. sci/smi control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 28. power state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 29. mechanical off to full on . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 30. soft off to full on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 31. general-purpose i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 32. fpic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
xiv list of figures AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 33. pic initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 34. priority cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 35. system-level implementation of apic components . . . . . 154 figure 36. wsc# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 37. osc waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 figure 38. pclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 figure 39. setup, hold, and valid delay timing diagram . . . . . . . . . . 302 figure 40. usbclk waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 figure 41. usb data waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 figure 42. bclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 figure 43. isa master interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 307 figure 44. isa 8-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . . 309 figure 45. isa 16-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . 311 figure 46. isa master-to-pci access timing . . . . . . . . . . . . . . . . . . . . . 313 figure 47. other isa master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 figure 48. dma read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 figure 49. dma write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 figure 50. type f dma interface timing . . . . . . . . . . . . . . . . . . . . . . . . 320 figure 51. eide pio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 figure 52. eide dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 figure 53. AMD-756 ? peripheral bus controller pin diagram . . . . . . 335 figure 54. 272 - pin pbga package preliminary specification . . . . . . 340 figure 55. 272 - pin pbga package preliminary specification, continued . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
list of tables xv 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information list of tables table 1. valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2. connecting pirq lines to pci int lines . . . . . . . . . . . . . . . . . 27 table 3. isa byte and word accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 4. i/o fixed address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 5. memory address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 6. rom decode control register . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 7. AMD-756 ? peripheral bus controller power planes. . . . . . . . 88 table 8. isa bus clock select bit programming . . . . . . . . . . . . . . . . . . . 89 table 9. ports 00h ? 0fh master dma controller . . . . . . . . . . . . . . . . . . . 92 table 10. ports 80h ? 8fh dma page register access . . . . . . . . . . . . . . . . 94 table 11. dma addressing for isa bus accesses (dma/slot bus) . . . . . 95 table 12. dma addressing for isa bus accesses (dma/pci ad bus) . . 96 table 13. type f dma control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 14. programming model for single target dma channel . . . . . . 100 table 15. dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 16. ide register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 17. ultra dma protocol modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 18. ultra dma interface signal redefinition . . . . . . . . . . . . . . . . 108 table 19. smm events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 20. power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 21. power transition times for figures above. . . . . . . . . . . . . . . 121 table 22. gpio output clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 23. rtc cmos addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 24. pci commands supported by the usbc . . . . . . . . . . . . . . . . . 132 table 25. power switching mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 26. host controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 27. register side effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 28. interrupt vector byte contents . . . . . . . . . . . . . . . . . . . . . . . . 144 table 29. polling status format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 30. slave dma controller registers . . . . . . . . . . . . . . . . . . . . . . . 158 table 31. master interrupt controller registers. . . . . . . . . . . . . . . . . . . 158 table 32. timer/counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
list of tables xvi 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 33. keyboard controller registers . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 34. cmos/rtc/nmi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 35. dma page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 36. system control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 37. slave interrupt controller registers . . . . . . . . . . . . . . . . . . . . 160 table 38. master dma controller registers . . . . . . . . . . . . . . . . . . . . . . 160 table 39. miscellaneous control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 40. interrupt controller level select. . . . . . . . . . . . . . . . . . . . . . . 160 table 41. pci control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 42. configuration space pci-to-isa header registers . . . . . . . . 161 table 43. isa bus control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 44. distributed dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 45. configuration space ide header registers . . . . . . . . . . . . . . 164 table 46. configuration space ide registers . . . . . . . . . . . . . . . . . . . . . 165 table 47. ide controller i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 48. configuration space power management header registers 166 table 49. configuration space power management registers . . . . . . . 167 table 50. basic power management control/status registers. . . . . . . . 169 table 51. processor power management registers. . . . . . . . . . . . . . . . . 169 table 52. general purpose power management registers. . . . . . . . . . . 169 table 53. generic power management registers . . . . . . . . . . . . . . . . . . 169 table 54. configuration space usb header registers . . . . . . . . . . . . . . 171 table 55. usb controller i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 56. keyboard controller register bit mapping . . . . . . . . . . . . . . 173 table 57. pci-isa bridge configuration (function 0) . . . . . . . . . . . . . . 177 table 58. ide configuration (function 1) . . . . . . . . . . . . . . . . . . . . . . . . 179 table 59. power management configuration (function 3) . . . . . . . . . . 180 table 60. usb configuration (function 4) . . . . . . . . . . . . . . . . . . . . . . . . 182 table 61. enhanced ide (eide) i/o registers . . . . . . . . . . . . . . . . . . . . 183 table 62. usb open hci memory-mapped registers. . . . . . . . . . . . . . . 184 table 63. power management i/o-mapped registers . . . . . . . . . . . . . . . 185 table 64. keyboard controller command codes . . . . . . . . . . . . . . . . . . 189 table 65. traditional port pin definition. . . . . . . . . . . . . . . . . . . . . . . . . 191 table 66. master dma controller ports 00h ? 0fh . . . . . . . . . . . . . . . . . . 192
list of tables xvii 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 67. slave dma controller ports c0h ? dfh. . . . . . . . . . . . . . . . . . . 193 table 68. dma page ports 80h ? 8fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 69. master interrupt controller ports 20h ? 21h . . . . . . . . . . . . . . . 194 table 70. slave interrupt controller ports a0h ? a1h . . . . . . . . . . . . . . . 194 table 71. timer/counter ports 40h ? 43h . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 72. cmos register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 73. picclk frequency and source . . . . . . . . . . . . . . . . . . . . . . . . 210 table 74. dma channel offset mapping . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 75. compatibility mode vs. native pci mode . . . . . . . . . . . . . . . . 215 table 76. udma extended timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 77. primary channel status register status bit meanings . . . . . 222 table 78. irq mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 79. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 80. i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 table 81. sm bus cycle type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 267 table 82. bit relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 83. delivery mode restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 84. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 85. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 86. usb dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 table 87. ide dc charateristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 table 88. ide driver types and required pull-ups . . . . . . . . . . . . . . . . 295 table 89. isa bus dc charateristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 table 90. pci bus dc charateristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 table 91. typical and maximum power dissipation . . . . . . . . . . . . . . . . 297 table 92. osc switching characteristics for 14.3182-mhz bus . . . . . . . 300 table 93. pclk switching characteristics for 33-mhz pci bus . . . . . . 301 table 94. pci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 table 95. usbclk switching characteristics for usb bus . . . . . . . . . . 303 table 96. bclk switching characteristics for 8-mhz bus . . . . . . . . . . . 305 table 97. isa master interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 306 table 98. isa 8-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . . . 308 table 99. isa 16-bit slave interface timing . . . . . . . . . . . . . . . . . . . . . . 310 table 100. isa master-to-pci access timing . . . . . . . . . . . . . . . . . . . . . . . 312
list of tables xviii 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 101. other isa master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 table 102. dma read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 table 103. dma write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 table 104. type f dma interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 319 table 105. eide pio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 table 106. eide dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 table 107. ultra dma-33 ide bus interface timing. . . . . . . . . . . . . . . . . 325 table 108. functional grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 table 109. i/o cell types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 table 110. state of pins at reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 table 111. multiplexed pins power up defaults. . . . . . . . . . . . . . . . . . . . 336 table 112. multiplexed pins determined by rom_kbcs# . . . . . . . . . . . 336 table 113. multiplexed pins selected by interrupt sources. . . . . . . . . . . 337 table 114. 272-pin pbga package preliminary specification . . . . . . . . . 339
revision history xix 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information revision history date rev description august 1999 b initial public release
xx revision history AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 1 features 1 22548b/0 ? august 1999 AMD-756? peripheral bus controller data sheet preliminary information 1 features the amd-750 ? chipset is a highly integrated system solution designed to deliver outstanding performance for the amd athlon ? processor and other amd athlon system interface-compatible processors. the amd-750 chipset consists of the amd-751 ? system controller and the AMD-756 ? peripheral bus controller. there is a block diagram of the amd-750 chipset in figure 1, on the following page. this document describes the features and operation of the AMD-756, which contains the following functional units: n integrated isa bus controller n enhanced master-mode pci ide controller with ultra dma-33/66 support n usb controller n keyboard/mouse controller n real-time clock there is a block diagram of the AMD-756 in figure 2, on page 8. key features of the AMD-756 controller are listed in this chapter. for a description of the amd-751, see the amd-751 system controller data sheet , order# 21910.
2 features chapter 1 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 1. amd-750? chipset system block diagram ethernet southbridge agp dram pci bus eide bus system management, reset, initialize, lan scsi 64-bit 64-bit agp bus 32-bit sdram memory bus preq# pgnt# system controller isa bus 16-bit bios amd athlon? processor amd-751? system controller AMD-756? peripheral bus controller interrupts smbus usbus
chapter 1 features 3 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 1.1 pc i-to-i sa bridge the AMD-756 controller includes a pc97-compliant pci-to-isa bridge with the following features: n pci 2.2-compliant interface n eight-level doubleword buffer between pci and isa buses n dual cascaded at-8259-compatible interrupt controllers n dual at-8237-compatible dma controllers n type f dma transfer support n support for isa legacy distributed dma across the pci bus n at-8254-compatible programmable interval timer n integrated real-time clock w/extended 256-byte cmos ram n programmable isa bus clock n fast reset and gate a20 operation n edge-triggered or level-sensitive interrupts n flash, 2-mbyte eprom, bios support n integrated keyboard controller with ps/2 mouse support 1.2 enhanced ide controllers the AMD-756 controller includes enhanced master mode pci and ide controllers with the following features: n ultra dma-33/66 support for a primary and secondary dual- drive port n transfer rates up to 33 mbytes per second supporting pio modes 1 ? 4, multi-word dma mode-2 drivers, and up to 66 mbytes per second supporting the ultra dma-66 interface n sixteen-level doubleword prefetch and write buffers n commands can be interleaved between the two channels n bus master programming interface for compliance with sff-8038i 1.0 and microsoft ? windows ? 95 n full-featured scatter-gather capability n support for atapi-compliant devices n support for pci-native and ata-compatibility modes n complete bus mastering software driver support
4 features chapter 1 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 1.3 universal serial bus controller the AMD-756 controller includes a universal serial bus (usb) controller with the following features: n usb 1.0 and ohci compliant n sixteen-level doubleword fifo for burst pci bus access n root hub and four ports n integrated physical-layer transceivers with over-current detection status on usb inputs n legacy keyboard and ps/2 mouse support 1.4 plug-n-play support the AMD-756 controller supports plug-n-play with the following features: n pci interrupts steerable to any of three interrupt channels n microsoft windows 98 and plug-n-play bios compliant n serial irq compliant 1.5 power management the AMD-756 controller includes the following sophisticated power management features: n supports advanced configuration and power interface power management (acpi 1.0 compliant) n supports legacy power management (apm 1.2 compliant) n supports soft-off and power-on suspend with hardware automatic wakeup n two general-purpose timers, one system-inactivity timer, and a 24-bit or 32-bit apci-compliant timer n dedicated external modem-ring input pin for system wakeup n normal, doze, sleep, suspend, and conserve modes n eighteen multiplexed general-purpose i/o pins
chapter 1 features 5 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information n smbus implementation for jedec-compatible dimm identification and on-board device power/thermal control n primary and secondary interrupt differentiation for individual channels n clock throttling control n multiple internal and external smi# sources for flexible power management
6 features chapter 1 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 2 overview 7 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 2 overview the AMD-756 peripheral bus controller includes three primary blocks, each with independent access to the pci bus, a complete set of pci interface signals and state machines, and capable of working independently with separate devices. these blocks are as follows: n a pci-to-isa bridge, which contains eight doubleword buffers and supports type f dma transfers to streamline pci bus operation and to comply with pci 2.1. these buffers allow for pseudo-split transactions, freeing the pci bus while isa transactions complete. n a usb controller interface with root hub and four ports with built-in physical layer transceivers n an eide controller master mode eide controller with full scatter-gather capability the AMD-756 also integrates many at-compatible and system control functions, including a keyboard controller with ps/2 mouse support and a real-time clock with extended 256-byte cmos ram. the pci mux block (see figure 2) determines which of the primary blocks accesses the pci bus as a master. it selects the appropriate set of pci output signals, and it enables the appropriate set of pci input signals. the mux block includes an arbiter which sets the priority of the primary blocks. the default priority scheme is as follows: 1. pci-to-isa (isa dma and distributed dma (ddma), and system management cycles) 2. usb 3. eide the priorities of the usb and eide controllers can be switched (through function 0, offset a4, bit 9[prisch]) to improve eide performance. distributed dma cycles and cycles to the system management registers are controlled by the pci state machines located in the pci-to-isa bridge. the usb and eide blocks each control
8 overview chapter 2 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information one group of configuration registers. the pci-to-isa bridge controls two sets of configuration registers ? one associated with the pci-to-isa bridge (including the ddma registers) and the other associated with the system management block. figure 2. AMD-756 ? peripheral bus controller block diagram pci muxing used to mux and demux pci interface signals among the 4 blocks usb controller usb root hub and four ports (pci function 4) ide controller (pci function 1) pci-to-isa bridge (pci function 0) distributed dma system management: power management, pnp, smbus, serial irq, and general purpose i/o (pci function 3) isa bus controller isa master control isa dma real-time clock (plus 256 bytes cmos ram) keyboard controller pit (isa timers) pic (isa interrupts) system management signals pci bus usb ports primary ide port secondary ide ports isa bus irq signals dma signals
chapter 2 overview 9 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 2.1 pci-to-isa bridge the AMD-756 peripheral bus controller offers both pci-compatible and isa-compatible bus interfaces. these interfaces, which are pci 2.1 compliant, control pci and isa bus communication. two main blocks (pci bus master and target blocks) make up the pci interface control. to become the pci bus master, the AMD-756 peripheral bus controller arbitrates for control of the bus with the amd-751 system controller. once bus ownership has been granted, the AMD-756 assumes pci bus master responsibility. the AMD-756 controller is in target mode when it does not own the pci bus. 2.1.1 pci bus master mode the AMD-756 controller arbitrates for bus ownership when an isa bus resource requests a dma-controlled transfer between memory and an i/o device or when an isa bus master requests bus ownership for data transfers. in both dma and isa master modes, data transfer takes place either between two isa bus resources or between an isa and a pci bus resource. the AMD-756 can determine the destination of a bus master request as follows: n by sampling an active devsel# input. this indicates that a particular target on the pci bus is responding to the current request. n by a positive decode of the master-driven address, as a target of an isa master transfer, to determine the internal destination. n by subtractive decode, when the access occurs between two isa bus resources. the AMD-756 controller pci interface translates all non-positive-decoded isa master requests to the pci bus. if the request is forwarded to the pci bus, the AMD-756 ensures isa and pci bus synchronization by controlling the isa-based iochrdy signal. if the devsel# signal is not received (sampled as active) within the specified time, the AMD-756 controller master interface assumes the requested cycle was
10 overview chapter 2 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information between isa resources and executes a pci master abort cycle. if the devsel# signal is received (sampled as active) within the specified time, the AMD-756 master interface executes a data transfer between the isa and pci buses. 2.1.2 pci bus target mode the AMD-756 peripheral bus controller stays in pci target mode when it does not own the bus. the target interface responds to any request from a pci resource by asserting devsel# if it positively decodes the current address as a destination either for the isa bus or the on-chip i/o. if the AMD-756 controller does not positively decode the current address, the AMD-756 target interface is deselected by an active devsel# input driven by another pci resource. if no active devsel# signal is received within a specified time, the AMD-756 acts as the subtractive decode resource by claiming all otherwise unclaimed pci bus requests and directing the request to the isa bus. to ensure correct data synchronization between the two buses on pci-to-isa write cycles, the isa command sequence begins only after the current pci master has indicated valid data on the bus by asserting irdy#. the AMD-756 responds to read requests (and write requests if the posted write buffer is disabled) destined for the isa bus or on-chip i/o by executing a single data transfer and signalling a target disconnect. if the AMD-756 controller samples an active devsel# input within a specified time, it is deselected, allowing the transfer to take place between the two pci resources. the AMD-756 can post pci-to-isa memory write cycles. if posting is enabled, the pci request is acknowledged immediately and the write data is latched to allow the isa cycle to proceed independently of the pci transaction.
chapter 2 overview 11 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 2.2 isa bus controller the integrated isa bus address latches and control logic allow the AMD-756 controller user to design a cost-effective system. in addition, the AMD-756 contains the decode logic to select an external keyboard controller. the AMD-756 device controls accesses to the bios and isa bus roms. the bios rom must be 8 bits. all other rom is accessed as either 8-bit or 16-bit rom residing on the isa bus, either on-board or off-board via the slots. accesses in the c0000h ? cffffh and e0000h ? effffh ranges can be defined as on-board system rom or off-board memory via the rom relocation register. the 82c37a-compatible dma controllers control data transfers between an i/o channel and on-board or off-board memory. the dma controllers can transfer data using 24-bit addressing (giving a 16-mbyte address space). internal latches latch the middle address bits from the dma controllers. a memory mapper generates the upper address bits. the distributed dma logic remaps i/o cycles to the legacy 82c37a-compatible dma controller. these cycles are converted by the AMD-756 into pci master accesses to another pci device (called the ddma target). function 0, offsets 6eh ? 60h specify individual enables for the dma channels and the addresses to which the legacy accesses are redirected. a further description of distributed dma (ddma) can be found in chapter 5. the AMD-756 controller generates synchronous isa bus timing and synchronous ide interface timing from the 33-mhz pci bus clock. the AMD-756 performs data steering functions between the isa and the pci buses. pci bus data accesses that are wider than those supported by the targeted isa bus device are automatically split into two, three, or four isa cycles. when pci bus reads are split, the data returned by the isa devices is assembled by latches before being returned to the pci bus. the AMD-756 controller also performs low-to-high and high-to-low byte swaps on the 16-bit bus.
12 overview chapter 2 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information as a pci target, the AMD-756 is capable of expanding pci accesses with non-contiguous byte enables into the appropriate discrete isa cycles. the AMD-756 controller functions are programmable through internal device-specific configuration registers. the state of various interface pins during power-on reset determines the default configuration. 2.3 eide controller the AMD-756 peripheral bus controller ? s enhanced ide controller provides a data path and control interface to standard ide drives. the block is compatible with the ansi ata specifications for ide hard disk operation. the bus mastering ide interface supports transfer rates up to and beyond mode-4 programmed i/o and mode-2 dma. two independent channels are supported, with the ability to connect to both channels with no external logic. data is transferred over independent 16-bit ide data buses. the AMD-756 peripheral bus controller ? s enhanced ide interface provides a variety of features to optimize system performance. a 16-doubleword write fifo and look-ahead read buffer support 32-bit pci data transfers. the ide-to-pci interface operates at pci speed and enhances system performance by allowing concurrent ide and pci operations. the dma bus-mastering state machine controls the iow# and ior# pulses for each ide channel during dma accesses. the AMD-756 contains two ide interfaces. channel 0 is the primary interface, with target i/o addresses at 1f0h ? 1f7h and 3f6h. the channel 0 irq pin is mapped to irq14. channel 1 is the secondary ide interface, with target i/o addresses at 170h ? 177h and 376h. the channel 1 irq pin is mapped to irq15. unless otherwise noted, when this document refers to one channel ? s resources the comments apply equally to the other channel. the master mode registers for both channels are contained in a single i/o block located at the i/o address specified by the contents of the bus master control registers base address
chapter 2 overview 13 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information register located at functions 1 and 2, offset 23h ? 20h. the first 8 bytes of the 16-byte block are associated with channel 0 and the second 8 bytes with channel 1 for each interface. independent configuration registers exist in pci configuration space for each channel. 2.4 universal serial bus (usb) the AMD-756 peripheral bus controller ? s usb host controller interface is compatible with both the usb 1.0 and the open host controller interface (ohic) specification. the interface uses two sets of software-accessible registers, pci configuration and usb i/o. the usb interface supports eighteen levels (doublewords) of data fifo and a root hub and four ports with built-in physical layer transceivers. the usb controller allows hot insertion of peripherals into the system with universal driver support. in addition, the AMD-756 offers an emulation mode for legacy keyboard and ps/2 mouse support. 2.5 power management the AMD-756 controller supports advanced configuration and power interface (acpi 1.0) as well as the legacy advanced power management (apm 1.2). in addition, AMD-756 power management is compatible with pc98 and onnow. the real-time clock with 256-byte extended cmos sram includes a data alarm and other enhancements for compatibility with the acpi standard. two sleep states are provided ? soft-off and power-on suspend ? as well as hardware automatic wake-up. additional power management features include event monitoring, processor clock throttling, hardware- based and software-based event handling, general purpose i/o, and external smi.
14 overview chapter 2 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 3. AMD-756 ? peripheral bus controller signal groups cpurst# ferr# ignne#/rtcirq# intr init# nmi smi# stpclk# bclk osc rstdrv ad[31:0] devsel# frame# irdy# pirq[d:a]# c/be[3:0]# par preq# pgnt# serr# stop# pclk trdy# idsel rtcx_in rtcx_out processor pci bus real-time rom_kbcs# universal usbclock usbp[3:0] usbn[3:0] usboc0# isa bus aen bale iocs16# ior# iow# irq15/nmsirq,irq14/nmpirq, la[23:17] memcs16# memr# memw# refresh# sbhe# spkr tc drq[7:5], drq[3:0] iochck# iochrdy sa[16:0] sd[15:0] smemr# smemw# enhanced ddackp# ddacks# ddrqp ddrqs diorp#/hdmardyp#/hstrobep diors#/hdmardys#/hstrobes diows#/stops drdyp#/ddmardyp#/dstrobep drdys#/ddmardys#/dstrobes suspend#/gpio4 diowp#/stopp keyboard ka20g/kbck dbrdy/gpio13 kbrc#/kbdt dack[7:5]#, dack[3:0]# pwrbtn# interface clock interface serial bus interface interface ide interface interface gpio14/ri# system management system management a20m# smbalert/ekirq12 pcirst# master# daddrp[2:0] daddrs[2:0] dcs1p# dcs1s# dcs3p# ddatas[15:0] bmreq#/gpio12 pme# pwrgd extirq8#/gpio3/ gpio2/ dcstop#/pnpirq2/gpio9 flagrd#/pnpdak#/gpio11 flagwr/pnpdrq/gpio10 intirq8#/sqwave/gpio16 pcistop#/pnpirq0/gpio7 msirq/gpio17/ smbusc/gpio0 smbusd/gpio1 interface irq12/smbalert#/usboc1, /extsmi# slpbtn# therm# picd1#/pitirq picd0#/kbcirq wsc#/sciirq picclk/usbirq irq11 ? 9,7 ? 3 pwron# ddatap[15:0] cpustop#/pnpcs1#/gpio6 cpusleep#/pnpcs0#/gpio5 cache_zz/pnpirq1/gpio8 c32khz/gpio15 dcs3s# serirq ekirq12/msdt ekirq1/msck /keylock
chapter 3 ordering information 15 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 3 ordering information amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. family/core table 1. valid combinations opn package type operating voltage case temperature AMD-756 272-pin bga 3.0 v ? 3.6 v 70 c notes: valid combinations are configurations that are or will be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. AMD-756
16 ordering information chapter 3 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 4 signal descriptions 17 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4 signal descriptions 4.1 signal terminology the following terminology is used in this chapter: n driven ? the processor actively pulls the signal up to the high voltage state or pulls the signal down to the low voltage state. n floated ? the signal is not being driven by the processor (high impedance state), which allows another device to drive this signal. n asserted ? for all active-high signals, the term asserted means the signal is in the high voltage state. for all active-low signals, the term asserted means the signal is in the low voltage state. n negated ? for all active-high signals, the term negated means the signal is in the low voltage state. for all active-low signals, the term negated means the signal is in the high voltage state. n sampled ? the processor measures the state of a signal at predefined points in time and takes the appropriate action based on the state of the signal. if a signal is not sampled by the processor, its assertion or negation has no effect on the operation of the processor. signals with pound signs (#) are active low.
18 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.2 processor interface 4.2.1 a20m# (processor a20 mask) output summary a20m# mask is the mask of processor address bit[20] to the processor. driven a20m# is the result of a logical or of the signals from the keyboard controller output port bit[1] (after being multiplexed between the internal and external keyboard controllers) and port92[a20en]. the keyboard controller output port bit defaults to high at reset and port92[a20en] defaults to low causing this pin to remain high after reset. 4.2.2 cpurst# (processor reset) output summary the AMD-756 peripheral bus controller asserts cpurst# to reset the processor during power-up. when pwrgd is low, cpurst# is asserted. cpurst# is negated 1.8 msecs after pwrgd is asserted. driven during power-up, rstdrv and pcirst# are driven inactive 1.8 msecs after pwrgd is driven active. cpurst# is driven inactive 1.5 secs later. cpurst# can be generated by writing a 1 to the configuration register function 0, offset 47, bit 0. this causes a pulse four pclk cycles long to be generated on pcirst# and rstdrv. cpurst# remains active for three additional pclk cycles. 4.2.3 ferr# (floating point error) input summary ferr# is asserted by the processor to indicate that the execution of a floating-point instruction caused the occurrence of an unmasked floating-point exception. this signal is tied to the ferr# signal on the processor.
chapter 4 signal descriptions 19 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information sampled if the processor ? s floating-point unit asserts ferr#, the AMD-756 generates an internal irq13, and asserts intr to the processor. irq13 continues to be asserted until a write to port f0h occurs. 4.2.4 ignne# (ignore numeric exception) output summary ignne# is connected to the ignore numeric exception signal on the processor. driven when ferr# is asserted, a write to port f0h asserts ignne#. ignne# is asserted until ferr# is negated. 4.2.5 init# (initialization) output summary the AMD-756 controller asserts init# if any of the following events occur: n a shut-down special cycle on the pci bus n a soft reset is initiated by the register n a write to port 92h bit 0 driven a pulse width of 1.0 to 1.5 secs is generated if function 0, offset 47, bit 7 is set. 4.2.6 intr (processor interrupt) output summary intr is driven by the AMD-756 peripheral bus controller to signal the processor that an interrupt request is pending and needs service.
20 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.2.7 nmi (non-maskable interrupt) output summary nmi is used to force a non-maskable interrupt to the processor. the AMD-756 peripheral bus controller generates an nmi when either serr# or iochk# is asserted. 4.2.8 smi# (system management interrupt) output summary smi# is asserted by the AMD-756 peripheral bus controller to alert the processor in response to selected power management events. 4.2.9 picclk (interrupt message bus clock) bidirectional summary by programming function 0, offset 4b [appiccks] bits, picclk can configured to be driven by the AMD-756 peripheral bus controller at the pclk frequency or slower. it can also be configured to be driven by an external component. this pin can also be used to reveal internal interrupts via function 0, offset 49 [rvlint] bit. 4.2.10 picd0# and picd1# (interrupt message data bits) bidirectional summary these pins are the ioapic message data bits. this pin can also be used to reveal internal interrupts via function 0, offset 49 [rvlint] bit.
chapter 4 signal descriptions 21 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.2.11 wsc# (write snoop complete) bidirectional summary this pin connects to the amd-751 system controller. it is used to signal that the most recent writes to system memory have made it to the coherent space. this signal requires an external 10-200 kohms pull-up resistor. this pin can also be used to reveal internal interrupts via function 0, offset 49 [rvlint] bit. 4.2.12 stpclk# (stop clock) output summary stpclk# is asserted by the AMD-756 peripheral bus controller to the processor in response to selected power management events. the processor control register function 3, offset 10h enables throttling and the duty cycle of stpclk#.
22 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.3 pci bus interface 4.3.1 ad[31:0] (pci address/data bus) summary bidirectional summary ad[31:0] are the standard pci address and data lines. they contain a physical address during the first clock of a pci transaction, and data during subsequent clocks. the address is driven when frame# is asserted, and data is driven or received in subsequent cycles. driven, sampled, and floated as outputs: when the AMD-756 peripheral bus controller is a pci master, it drives these signals with valid address or data off the rising edge of pclk. during the first clock that frame# is asserted these signals contain address. during subsequent clocks these signals contain data. ad[31:0] become tri-stated at the end of the data phase. as inputs: when the AMD-756 peripheral bus controller is a pci slave, these lines are inputs during the address and write data phases of a transaction. the AMD-756 peripheral bus controller samples these signals on the rising edge of pclk. during the first clock after frame# is asserted the bus controller loads the bus contents into the internal address register. on each subsequent clock in which both trdy# and irdy# are asserted the bus controller loads data into the data fifo. ad[31:0] are floated for one clock in between the address phase and the data phase of a read transfer. ad[31:0] are also floated during reset and when no initiator is driving the bus. 4.3.2 c/be[3:0]# (pci command/byte enable) bidirectional summary during the first clock of a pci transaction, when frame# is asserted, these lines contain the pci bus command (c[3:0]). on subsequent clocks, these lines contain pci byte enables (be[3:0]#) corresponding to supplied or requested data.
chapter 4 signal descriptions 23 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information driven, sampled, and floated as outputs: be[3:0]# are outputs when the AMD-756 peripheral bus controller is a master. during the address phase of the transaction, c/be[3:0] define the bus command and are asserted when frame# is asserted. c/be[3:0] are used as byte enables and are asserted during the data phase. c/be[3:0] become tri-stated at the end of data phase. as inputs: when the AMD-756 peripheral bus controller is a slave, it samples these lines on the rising edge of pclk. if frame# is asserted, then the bus carries command information. c/be[3:0]# are floated during reset and when no initiator is driving the bus. 4.3.3 devsel# (pci bus device select) bidirectional summary devsel# indicates either that the driving device is the target of the current access or whether any device on the bus has responded to the current address. driven, sampled, and floated as output: when the AMD-756 is not a pci bus master, it defaults to target mode, and devsel# is an output indicating that the AMD-756 claims a pci transaction through either positive or subtractive decoding. in a positive decode, the AMD-756 controller asserts devsel# one pclk cycle after frame# is sampled active and holds devsel# low through the end of the transaction. in a subtractive decode, devsel# is asserted three pclk cycles after frame# is asserted. positive and negative decoding are explained in section 5.1. as input: when the AMD-756 peripheral bus controller is a pci bus master, devsel# is an input that indicates whether a slave has responded to the current address. if devsel# is sampled inactive in the fourth pclk cycle after frame# is asserted, the AMD-756 aborts the pci bus cycle. devsel# is floated during reset and when no initiator is driving the bus.
24 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.3.4 frame# (pci bus cycle frame) bidirectional summary asserting frame# indicates the address phase of a pci transfer, and its negation indicates that the cycle initiator wants one more data transfer. while frame# is asserted, data transactions can continue. when frame# is negated, data transactions are in the final phase. driven, sampled, and floated as output: when the AMD-756 peripheral bus controller is a pci bus master, frame# is asserted at the beginning of a pci cycle and is held asserted until the beginning of the last data transfer in the cycle. as input: when the AMD-756 peripheral bus controller is a slave, it samples and latches the c/be[3:0]# and ad[31:0] signals and asserts devsel# at the first pclk on which frame# is asserted. frame# is floated during reset and when no initiator is driving the bus. 4.3.5 idsel (pci initialization device select) input summary idsel is used as a chip select during configuration read and write cycles. sampled idsel is sampled at the rising edge of pclk when frame# is asserted. 4.3.6 irdy# (pci bus initiator ready) bidirectional summary irdy# is asserted by a pci initiator from the first clock cycle after frame# is asserted to the last clock of the transaction to indicate that the initiator is ready for data transfer. irdy# asserted during a read cycle indicates the master is ready to accept data. irdy# asserted during a write cycle indicates that
chapter 4 signal descriptions 25 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information write data on ad[31:0] is valid. data is transferred on the pci bus on each pclk in which both irdy# and trdy# are asserted. wait states are inserted on the bus until both irdy# and trdy# are asserted together. driven, sampled, and floated as output: when acting as a pci bus master, the AMD-756 peripheral bus controller asserts irdy# one pclk after asserting frame# and holds irdy# asserted until one cycle before the last data transactions. the AMD-756 does not complete a read or write cycle until both irdy# and trdy# are sampled asserted. as input: when acting as a pci slave, the AMD-756 peripheral bus controller samples irdy# on every rising edge of pclk. when irdy# and trdy# are both asserted, the bus controller accepts the data. if either signal is negated, the current data is held on the bus. irdy# is floated when no bus master is currently driving the bus. 4.3.7 par (pci bus parity) bidirectional summary par, when asserted, indicates even parity. when acting as a pci master, the AMD-756 peripheral bus controller drives par one clock after the address phase and one clock after each data write phase to indicate even parity across ad[31:0] and c/be[3:0]#. when acting as a pci target, the AMD-756 drives par one clock after each data read phase. driven, sampled, and floated as output: when the AMD-756 peripheral bus controller is driving data on ad[31:0], par is driven one pclk after an address, read, or write data phase. as input: when the AMD-756 peripheral bus controller is accepting data on ad[31:0], par is sampled one clock cycle after a read is completed. par is only floated when changing bus ownership from one initiator to another.
26 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.3.8 pcirst# (pci reset) output summary pcirst# is a reset signal for the pci bus. the AMD-756 peripheral bus controller can assert reset during power-up. a pci reset can be forced during normal operation by setting configuration register function 0, offset 47h, bit 0. driven during power-up, pcirst# is negated 1.8 msecs after pwrgd is asserted. pcirst# can also be generated by setting the configuration register function 0, offset 47, bit 0. a pulse four pclk cycles long is generated on pcirst#. 4.3.9 pclk (pci bus clock) input summary pclk provides timing for all transactions on the pci bus. all signals except pcirst# and pirq[d:a]# are sampled on the rising edge of pclk, and all timing parameters are defined with respect to this edge. pclk runs at a frequency up to 33 mhz. pclk can be divided down to generate the isa bus clock. 4.3.10 pgnt# (pci grant) input summary the amd-751 system controller asserts pgnt# to grant pci bus access to the AMD-756 peripheral bus controller. sampled pgnt# is sampled at the rising edge of pclk. if pclk is asserted, the AMD-756 takes control of the bus.
chapter 4 signal descriptions 27 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.3.11 pirq[d:a]# (pci interrupt requests) input summary interrupts on the pci bus are asserted low and are asynchronous. after an interrupt is asserted, it should remain asserted until the device driver clears the pending request. these pins are typically connected to the pci bus int lines as shown in table 2. sampled pirq[d:a]# are sampled at the rising edge of pclk. 4.3.12 preq# (pci request) output summary the AMD-756 peripheral bus controller asserts preq# to request control of the pci bus. driven preq# is driven off of the rising edge of pclk. reset forces preq# inactive. preq# is always driven. 4.3.13 serr# (system error) input summary serr# reports address parity errors and data parity errors on the special cycle command. serr# is a synchronous signal. any pci device that detects a system error condition can alert the system by asserting serr# for one pci clock. serr# has no timing relationship to any pci transaction. sampled serr# is sampled at the rising edge of pclk. table 2. connecting pirq lines to pci int lines pirqa# pirqb# pirqc# pirqd# pci slot 1 inta# intb# intc# intd# pci slot 2 intb# intc# intd# inta# pci slot 3 intc# intd# inta# intb# pci slot 4 intd# inta# intb# intc#
28 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.3.14 stop# (stop) bidirectional summary a pci target asserts stop# to request that the master stop the current transaction. driven, sampled, and floated as output: when acting as a pci slave, the AMD-756 peripheral bus controller asserts stop# and trdy# simultaneously to indicate a target disconnect following the data transfer or burst. stop# is not asserted if the transfer is a single, non-bursted transfer. as input: when acting as a pci bus master, stop# causes the AMD-756 peripheral bus controller to terminate the data transfer and either to abort or to retry the transfer depending on the state of devsel# and trdy#. stop# is sampled on every rising edge of pclk in the data phase of a transaction. stop# is floated during reset and when not being asserted by a target. 4.3.15 trdy# (pci target ready) bidirectional summary trdy# indicates that the target agent can complete the current data phase of the transaction. driven, sampled, and floated as output: as a pci slave, the AMD-756 peripheral bus controller asserts trdy# to indicate it has sampled the data from the pci address/data bus during a write phase, or presented valid data on the bus during a read phase. as input: a pci target asserts trdy# when ready for data transfer. when the AMD-756 peripheral bus controller is the pci bus master, trdy# is an input that indicates that the target device can complete the data phase of the transaction. after a pci bus transaction is initiated, the AMD-756 peripheral bus controller inserts wait cycles until trdy# is sampled active. trdy# is sampled on every rising edge of pclk in the data phase, and is floated when no bus master is driving the bus.
chapter 4 signal descriptions 29 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.4 isa bus interface 4.4.1 aen (address enable) output summary aen is asserted during dma transfer cycles to the i/o resources on the bus to prevent i/o slaves from misinterpreting dma cycles as valid i/o cycles. driven aen is asserted only when the dma controller is the bus owner. 4.4.2 bale (bus address latch enable) output summary bale is asserted for one bus clock at the beginning of any bus cycle initiated by a pci master. driven bale is asserted by the AMD-756 peripheral bus controller to indicate that the address signal lines (sa[19:0], la[23:17], and sbhe#) are valid. 4.4.3 bclk (bus clock) output summary bclk is the reference clock for the isa bus, and is derived either by dividing pclk by 2, 3, 4, 5, 6, 10, or 12, or by dividing osc by 2. bclk timing is controlled by programming the isa clock control register, function 0, offset 42h. bit 3 of that register, the isa clock select enable bit, is cleared at reset, forcing bclk to default to the value equal of pclk/4. driven bclk is always active.
30 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.4.4 dack[7:5]#, dack[3:0]# (dma acknowledge) output summary these signals, when asserted, indicate that the corresponding request for dma service has been granted. driven the signal is asserted before i/o and memory command lines are asserted and stays asserted until the end of the dma cycle. 4.4.5 drq[7:5], drq[3:0] (dma request) input summary these asynchronous dma request lines are used by external devices to request services from the AMD-756 peripheral bus controller dma controller. drq[3:0] is used for transfers between 8-bit i/o adapters and system memory. drq[7:5] is used for transfers between 16-bit i/o adapters and system memory. drq4 is not available externally. sampled these signals are sampled at the rising edge of bclk. 4.4.6 iochck# (i/o channel check) input summary iochck# is asserted by a device or memory on the isa bus to indicate that a parity error or other uncorrectable error has occurred. if i/o checking is enabled and iochck# is sampled asserted, the AMD-756 peripheral bus controller generates an nmi to the processor. sampled iochck# is sampled at the rising edge of bclk.
chapter 4 signal descriptions 31 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.4.7 iochrdy (i/o channel ready) bidirectional summary devices on the isa bus negate iochrdy to indicate that additional time is required to complete the cycle. the cycle can be generated by the processor, dma controllers, or the refresh controller. the AMD-756 peripheral bus controller responds by inserting wait states to add more time to the cycle. the default number of wait states for cycles initiated by the processor is as follows: n 8-bit peripherals 4 wait states n 16-bit peripherals 1 wait state n rom cycles 3 wait states n dma cycles 1 dma wait state any peripheral that cannot present read data or strobe in write data in this amount of time must assert iochrdy to extend these cycles. the AMD-756 peripheral bus controller always drives iochrdy low in either dma or master mode to allow for pci bus latency. this signal is an input while pwrgd is low and used to select the state of function 3, offset 48 [nmlrst]. sampled iochrdy is sampled at the rising edge of bclk when i/o or memory command lines are active. 4.4.8 iocs16# (16-bit i/o chip select) input summary iocs16# is driven by i/o devices on the isa bus to indicate that they support 16-bit i/o bus cycles. the AMD-756 peripheral bus controller samples iocs16# to determine when a processor access requires a 16-bit to 8-bit conversion. the AMD-756 peripheral bus controller also performs a conversion if iocs16# is sampled high and a 16-bit i/o cycle is requested. in a conversion, the AMD-756 inserts a command delay of one bus cycle and the cycle becomes four wait states long.
32 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information sampled iocs16# is sampled at the rising edge of bclk when i/o or memory command lines are active. if iocs16# is sampled low, the AMD-756 peripheral bus controller performs an i/o access in one wait state, inserting one command delay. 4.4.9 ior# (i/o read) bidirectional summary ior# is the command to an isa i/o slave device indicating the slave can drive data onto the isa data bus. driven, sampled, and floated as output: during dma transfers, ior# is driven by the dma controller. ior# is inactive during a refresh cycle. as input: ior# is an input when the AMD-756 peripheral bus controller is bus master and an output at all other times. when the AMD-756 is a pci slave, ior# is driven by the internal isa bus controller. 4.4.10 iow# (i/o write) bidirectional summary iow# is the command to an isa i/o slave device indicating the slave can latch data from the isa data bus. driven, sampled, and floated as output: during dma transfers, iow# is driven by the dma controller. iow# is inactive during a refresh cycle. as input: iow# is an input when the AMD-756 peripheral bus controller is bus master and an output at all other times. when the AMD-756 is a pci slave, iow# is driven by the internal isa bus controller. 4.4.11 irq15, irq14, irq[12:9], irq[7:3] (interrupt requests) input summary the irq signals provide both system board components and isa bus i/o devices with a mechanism for asynchronously interrupting the processor. sampled irqs are sampled at the rising edge of bclk.
chapter 4 signal descriptions 33 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.4.12 nmpirq (native mode primary ide port irq) input summary this pin is multiplexed with irq14 and is selected by setting function 1, offset 8, bit 8. nmpirq is an active high, shared interrupt that is logically combined with pirqa# such that it can be shared with other pci devices. 4.4.13 nmsirq (native mode secondary ide port irq) input summary this pin is multiplexed with irq15 and is selected by setting function 1, offset 8, bit 10. nmsirq is an active high, shared interrupt that is logically combined with pirqa# such that it can be shared with other pci devices. 4.4.14 la[23:17] (unlatched address) bidirectional summary the la[23:20] address lines are bidirectional and allow accesses to physical memory on the isa bus up to 16 mbytes. the la[19:17] are connected to sa[19:17] pins on the isa connector. driven, sampled, and floated as outputs: the la pins are output when master# is high. the value driven on the la bus is the address stored in the ad address register during pci-initiated cycles and the refresh counter during non-isa bus master refresh cycles. as inputs: the la pins are input when master# is low. 4.4.15 master# (isa master cycle indicator) input summary an external bus master device asserts master# to indicate that it has control of the bus. sampled master# is sampled at the beginning of an isa bus cycle.
34 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.4.16 memcs16# (16-bit memory chip select) input summary isa 16-bit slave memory devices drive this line low to indicate support for 16-bit memory bus cycles. sampled this line is sampled to determine when a 16-bit to 8-bit conversion is needed for processor accesses. conversion is performed when the AMD-756 peripheral bus controller requests a 16-bit memory cycle and memcs16# is sampled high. a command delay of one clock cycle is inserted, and the cycle becomes four wait states long. if memcs16# is sampled low, a memory access is performed in one wait state with no command delays inserted. memcs16# is ignored for dma and refresh cycles. 4.4.17 memr# (memory read) bidirectional summary memr# is the command to an isa memory slave device indicating that it can drive data onto the isa data bus. driven, sampled, and floated as output: the memory read command signal is asserted after bale is asserted until the end of the command. memr# is driven during memory, dma, or isa master cycles. as input: this signal is an input when an external bus master is in control. 4.4.18 memw# (memory write) bidirectional summary memw# is the command to an isa memory slave device indicating that it can latch data from the isa data bus. driven, sampled, and floated as output: the memory write command signal is asserted after bale is asserted until the end of the command. memw# is driven during memory, dma, or isa master cycles. as input: this signal is an input when an external bus master is in control.
chapter 4 signal descriptions 35 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.4.19 osc (oscillator) input summary osc is a 14.31818-mhz clock used by the internal timers and the acpi timer. it can also be used as the source for bclk. 4.4.20 refresh# (refresh) bidirectional summary refresh#, when asserted, indicates a refresh cycle is in progress. it enables the sa[7:0] address to drive the row address of the dram on the isa bus. dram is refreshed when memr# is asserted. driven, sampled, and floated as output: refresh# indicates a refresh cycle is in progress. it is asserted by the AMD-756 peripheral bus controller whenever a refresh cycle is initiated. this signal is driven directly to the isa bus. as input: refresh# is driven by 16-bit isa bus masters to indicate a refresh cycle. 4.4.21 rom_kbcs# (rom and keyboard chip select) output summary during isa memory cycles, rom_kbcs# is the chip select to the rom bios. during isa i/o cycles rom_kbcs# is the chip select to the external keyboard controller. 4.4.22 rstdrv (reset drive) output summary rstdrv is the reset signal to the isa bus. it is generated from the received rst signal and is synchronized to pclk, though it is used for the isa bus. driven during power-up, rstdrv is inactive 1.8 msecs after pwrgd is driven active. rstdrv can also be generated by writing a 1 to the configuration register function 0, offset 47, bit 0. a pulse of four pclk cycles long is generated on rstdrv.
36 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.4.23 sa[16:0] (system address bus) bidirectional summary sa[16:0] address lines, together with la[23:17], are used to access physical memory on the isa bus. in i/o accesses, only sa[15:0] are used. driven, sampled, and floated as output: sa[16:0] are output when the AMD-756 peripheral bus controller owns the bus and are driven valid when bale is asserted. as input: sa[16:0] are inputs when an isa master owns the isa bus. 4.4.24 sbhe# (system byte high enable) bidirectional summary when asserted, sbhe# indicates that a byte is being transferred on the upper byte of the isa data bus (sd[15:8]). sbhe# is negated during refresh cycles. 4.4.25 sd[15:0] (isa system data) bidirectional summary sd[15:0] provide the data path for devices residing on the isa bus. the low order isa lines, sd[7:0], are connected to xd[7:0]. 4.4.26 smemr# (standard memory read) output summary smemr# is the command that permits a slave to drive data residing below the 1-mbyte region onto the isa data bus. driven smemr# is driven during memory, dma, or isa master cycles. smemr# is a delayed version of memr#.
chapter 4 signal descriptions 37 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.4.27 smemw# (standard memory write) output summary smemw# is the command that permits a slave to latch data residing below the 1-mbyte region from the isa data bus. driven smemw# is driven during memory, dma, or isa master cycles. smemw# is a delayed version of memw#. 4.4.28 spkr (speaker) bidirectional summary spkr is the output of counter 2 for the speaker. this signal is an input while pwrgd is low and is used to select the state of function 3, offset 48 [enide, enpci, enisa]. 4.4.29 tc (terminal count) output summary the AMD-756 peripheral bus controller asserts tc to dma slaves to indicate that one of the dma channels has transferred all data.
38 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.5 ultra dma enhanced ide interface 4.5.1 daddrp[2:0] (primary ide address) output summary daddrp[2:0] is the ide controller primary port address. it addresses the ata command or control block. driven daddrp[2:0] is driven before the read or write command signals are asserted to satisfy the address setup time of the ide drives. 4.5.2 daddrs[2:0] (secondary ide address) output summary daddrs[2:0] is the ide controller secondary port address. it addresses the ata command or control block. driven daddrs[2:0] is driven before the read or write command signals are asserted to satisfy the address setup time of the ide drives. 4.5.3 dcs1p# (primary port chip select) output summary dcs1p# is the primary port chip select 1xx. this is active during accesses to the address space specified by function 1, offset 10h, which defaults to i/o addresses 1f7h - 1f0h. driven dcs1p# is driven before the read or write command signals are asserted to satisfy the disk chip select setup time of the ide drives.
chapter 4 signal descriptions 39 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.5.4 dcs1s# (secondary port chip select) output summary dcs1s# is the secondary port chip select 1xx. this is active during accesses to the address space specified by function 1, offset 18h, which defaults to i/o addresses 177h - 170h. driven dcs1s# is driven before the read or write command signals are asserted to satisfy the disk chip select setup time of the ide drives. 4.5.5 dcs3p# (primary port chip select) output summary dcs3p# is the primary port chip select 3xx. this is active during accesses to the address space specified by function 2, offset 14h, which defaults to i/o addresses 3f7h - 3f4h. driven dcs3p# is driven before the read or write command signals are asserted to satisfy the disk chip select setup time of the ide drives. 4.5.6 dcs3s# (secondary port chip select) output summary dcs3s# is the secondary port chip select 3xx. this is active during accesses to the address space specified by function 2, offset 1ch, which defaults to i/o addresses 377h - 374h. driven dcs3s# is driven before the read or write command signals are asserted to satisfy the disk chip select setup time of the ide drives. 4.5.7 ddatap[15:0] (primary ide data bus) bidirectional summary ddatap[15:0] transfers data to or from the primary ide device.
40 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information driven, sampled, and floated as outputs: when the AMD-756 peripheral bus controller is writing to an ide device, ddatap[15:0] is driven valid before the negation of the diowp# command. as inputs: when the AMD-756 peripheral bus controller is reading from an ide device, ddatap[15:0] is sampled at the rising edge of the diorp# command. ddatap[15:0] is tri-stated when no read or write command is in process. 4.5.8 ddatas[15:0] (secondary ide data bus) bidirectional summary ddatas[15:0] transfers data to or from the secondary ide device. driven, sampled, and floated as outputs: when the AMD-756 peripheral bus controller is writing to an ide device, ddatas[15:0] is driven valid before the negation of the diows# command. as inputs: when the AMD-756 peripheral bus controller is reading from an ide device, ddatas[15:0] is sampled at the rising edge of the diors# command. ddatas[15:0] is tri-stated when no read or write command is in process. 4.5.9 ddackp# (primary ide dma acknowledge) output summary ddackp# is the primary ide channel dma acknowledge. the AMD-756 peripheral bus controller responds to ddrqp either to acknowledge that data has been accepted or to inform that data is available. driven ddackp# is driven at the rising edge of pclk after sampling ddrqp asserted.
chapter 4 signal descriptions 41 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.5.10 ddacks# (secondary ide dma acknowledge) output summary ddacks# is the secondary ide channel dma acknowledge. the AMD-756 peripheral bus controller responds to ddrqs either to acknowledge that data has been accepted or to inform that data is available. driven ddacks# is driven at the rising edge of pclk after sampling ddrqs asserted. 4.5.11 ddmardyp# (primary device dma ready, ultra dma mode) input summary ddmardyp# is the primary channel flow control signal for output data bursts, and shares the same pin with drdyp#. when ready to receive dma data, a device asserts ddmardyp#. the device negates ddmardyp# to pause an ultra dma output data transfer. sampled ddmardyp# is sampled at the rising edge of internal pclk. 4.5.12 ddmardys# (secondary device dma ready, ultradmamode) input summary ddmardys# is the secondary channel flow control signal for output data bursts. it shares the same pin with drdys#. when ready to receive dma data, a device asserts ddmardys#. the device negates ddmardys# to pause an ultra dma output data transfer. sampled ddmardys# is sampled at the rising edge of internal pclk. 4.5.13 ddrqp (primary ide dma request) input summary ddrqp is the primary ide channel dma request. when ready to read or write dma data, a device asserts ddrqp. sampled ddrqp is sampled at the rising edge of pclk.
42 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.5.14 ddrqs (secondary ide dma request) input summary ddrqs is the secondary ide channel dma request. when ready to read or write dma data, a device asserts ddrqs. sampled ddrqs is sampled at the rising edge of pclk. 4.5.15 diorp# (primary i/o read) output summary diorp# is the primary ide channel drive read strobe. the falling edge of diorp# enables the transfer of data from a register or data port of the drive onto the ide data bus, ddatap[15:0]. driven the rising edge of diorp# latches the data. 4.5.16 diors# (secondary i/o read) output summary diors# is the secondary ide channel drive read strobe. the falling edge of diors# enables the transfer of data from a register or data port of the drive onto the ide data bus, ddatas[15:0]. driven the rising edge of diors# latches the data. 4.5.17 diowp# (primary i/o write) output summary diowp# is the primary ide channel drive write strobe. driven the rising edge of diowp# clocks data from the ide data bus (ddatap[15:0]) into either a register or the data port of the drive.
chapter 4 signal descriptions 43 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.5.18 diows# (secondary i/o write) output summary diows# is the secondary ide channel drive write strobe. driven the rising edge of diows# clocks data from the ide data bus (ddatas[15:0]) into either a register or the data port of the drive. 4.5.19 drdyp# (primary device ready) input summary drdyp# is the primary channel device ready indicator. if a device is not ready to respond to a data transfer request, the device negates drdyp# to extend the AMD-756 peripheral bus controller read or write cycle. when negated, drdyp# is in a high impedance state. sampled drdyp# is sampled at the rising edge of pclk. 4.5.20 drdys# (secondary device ready) input summary drdys# is the secondary channel device ready indicator. if a device is not ready to respond to a data transfer request, the device negates drdys# to extend the AMD-756 peripheral bus controller read or write cycle. when negated, drdys# is in a high impedance state. sampled drdys# is sampled at the rising edge of pclk.
44 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.5.21 dstrobep (primary device strobe, ultra dma mode) input summary dstrobep and drdyp# share the same pin. dstrobep is the primary channel input data strobe signal from the device for an ultra dma input data transfer. both edges of dstrobep latch data from ddatap[15:0] into the host. the device may stop toggling dstrobep to pause an ultra dma data in transfer. sampled dstrobep is sampled at the rising edge of pclk. 4.5.22 dstrobes (secondary device strobe, ultra dma mode) input summary dstrobes and drdys# share the same pin. dstrobes is the secondary channel input data strobe signal from the device for an ultra dma input data transfer. both edges of dstrobes latch data from ddatas[15:0] into the host. the device may stop toggling dstrobes to pause an ultra dma data in transfer. sampled dstrobes is sampled at the rising edge of pclk. 4.5.23 hdmardyp# (primary host dma ready, ultra dma mode) output summary hdmardyp# and diorp# share the same pin. hdmardyp# is the primary channel flow control signal for ultra dma input data bursts and is asserted when the host is ready to receive dma data. the host negates hdmardyp# to pause an ultra dma data in transfer. driven hdmardyp# is asserted after the ide device asserts ddackp# to signal that the host is ready to receive data.
chapter 4 signal descriptions 45 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.5.24 hdmardys# (secondary host dma ready, ultra dma mode) output summary hdmardys# and diors# share the same pin. hdmardys# is the secondary channel flow control signal for ultra dma input data bursts, and is asserted when the host is ready to receive dma data. the host negates hdmardys# to pause an ultra dma data in transfer. driven hdmardys# is asserted after the ide device asserts ddacks# to signal that the host is ready to receive data. 4.5.25 hstrobep (primary host strobe, ultra dma mode) output summary hstrobep and diorp# share the same pin. hstrobep is the primary channel strobe signal from the host for an ultra dma output data transfer. both edges of hstrobep latch data from ddatap[15:0] into the device. the host may stop toggling hstrobep to pause an ultra dma output data transfer. driven hstrobep is driven after the ide device asserts ddmardyp# to signal that it is ready to receive data. 4.5.26 hstrobes (secondary host strobe, ultra dma mode) output summary hstrobes and diors# share the same pin. hstrobes is the secondary channel strobe signal from the host for an ultra dma output data transfer. both edges of hstrobes latch data from ddatap[15:0] into the device. the host may stop toggling hstrobes to pause an ultra dma output data transfer. driven hstrobes is driven after the ide device asserts ddmardys# to signal that it is ready to receive data.
46 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.5.27 stopp output summary stopp and diowp# share the same pin. stopp halts data transfer in the primary channel. driven the host asserts stopp before an ultra dma burst is initiated and negates stopp before an ultra dma burst is transferred. the host asserts stopp during or after data transfers in ultra dma mode to signal the termination of the burst. 4.5.28 stops output summary stops and diows# share the same pin. stops halts data transfer in the secondary channel. driven the host asserts stops before an ultra dma burst is initiated and negates stops before an ultra dma burst is transferred. the host asserts stops during or after data transfer in ultra dma mode to signal the termination of the burst.
chapter 4 signal descriptions 47 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.6 system management pins 4.6.1 c32khz output summary the c32khz clock is available in the fon, c2, c3, and pos power states and is not available in the soff or moff states. this pin can also be configured as gpio15 by the i/o mapped register (base pointer: function 3, offset 58h), offset cfh. 4.6.2 cache_zz output summary when cache_zz is connected to the zz input of the second- level cache, the second-level cache enters sleep mode. cache_zz can be asserted in the c2, c3, or pos states if enabled by function 3, offset 50h. this pin can also be configured as gpio8 by the i/o mapped register (base pointer: function 3, offset 58h), offset c8h. 4.6.3 pnpirq1 (plug and play interrupt request 1) input summary pnpirq1 and cache_zz share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset c8h. pnpirq1 can be assigned to control any of the 12 internal isa irq signals and is configured by function 3, offset 44h. 4.6.4 cpusleep# output summary when connected to the sleep pin, asserting cpusleep# places the processor into a non-snoop-capable low power state. this signal can be asserted in the c2, c3, or pos states if enabled by function 3, offset 50h. cpusleep# can also be configured as gpio5 by the i/o mapped register (base pointer: function 3, offset 58h), offset c5h.
48 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.6.5 pnpcs0# (plug and play chip select 0) output summary pnpcs0# and cpusleep# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset c5h. this signal is used as a programmable chip select to external isa bus devices. pnpcs0# is active during isa bus cycles to memory space or i/o space as specified by function 3, offset 46h[cs0m and cs0is]. 4.6.6 cpustop# (processor clock stop) output summary cpustop# is connected to the system pll clock chip to control the host clock signals. cpustop# can be asserted in the c2, c3, or pos states if enabled by function 3, offset 50h. this pin can also be configured as gpio6 by the i/o mapped register (base pointer: function 3, offset 58h), offset c6h. 4.6.7 pnpcs1# (plug and play chip select 1) output summary pnpcs1# and cpustop# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset c6h. this signal is used as a programmable chip select to external isa bus devices. pnpcs1# is active during isa bus cycles to memory space or i/o space as specified by function 3, offset 46h [cs1m and cs1is]. 4.6.8 dcstop# (dram controller stop) output summary dcstop# is connected to the sleep pin of the amd-751 system controller and is asserted when the host clock is stopping. this enables an alternative dram refresh scheme to start. dcstop# can be asserted in the c2, c3, or pos states if enabled in function 3, offset 50h. this pin can also be configured as gpio9 by the i/o mapped register (base pointer: function 3, offset 58h), offset c9h.
chapter 4 signal descriptions 49 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.6.9 pnpirq2 (plug and play interrupt request 2) input summary pnpirq2 and dcstop# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset c9h. this signal can be assigned to control any of the 12 internal isa irq signals by function 3, offset 44h. 4.6.10 extsmi# (external smi input) input summary extsmi# can be used to generate smi or sci interrupts and resume events. this pin can also be configured as gpio12 by the i/o mapped register (base pointer: function 3, offset 58h), offset cch. 4.6.11 bmreq# (pci bus master request) input summary bmreq# and extsmi# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset cch. this signal is the or of the external pci bus request signals. this function drives the i/o mapped register (base pointer: function 3, offset 58h), offset 00h[bm_sts] status bit if selected by the i/o mapped register (base pointer: function 3, offset 58h), offset cch. if this function is not selected by the i/o mapped register (base pointer: function 3, offset 58h), offset cch, frame# is used to drive the status bit. bmreq# is not guaranteed to meet minimum setup time to the pci clock and is treated as an asynchronous input. 4.6.12 flagrd# (flag read) output summary flagrd# is connected to the output-enable input of one or two external 244-like buffers. the inputs to the external buffers are flags designating which processor read access is required. the outputs drive onto the isa data bus. flagrd# is asserted during reads of the i/o mapped register (base pointer:
50 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information function 3, offset 58h), offset 1ah register so that the external latch inputs are read back to the pci bus. this pin can also be configured as gpio11 by the i/o mapped register (base pointer: function 3, offset 58h), offset cbh. 4.6.13 pnpdak# (plug and play dma acknowledge) output summary pnpdak# and flagrd# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset cbh. this pin can be controlled by any of the dack[7:5, 3:0]# pins that are outputs of the internal dma controller and is configured by function 3, offset 46h[dmasel]. 4.6.14 flagwr (flag write) output summary flagwr is connected to the latch-enabled input of one or two external 373-like latches. the inputs to the external latches are driven by the isa data bus; the outputs are flags that can be latched off the isa bus during writes to the i/o mapped register (base pointer: function 3, offset 58h), offset 18h register. this pin can also be configured as gpio10 by the i/o mapped register (base pointer: function 3, offset 58h), offset cah. 4.6.15 pnpdrq (plug and play dma request) input summary pnpdrq and flagwr share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset cah. pnpdrq can be assigned to control any of the drq[7:5, 3:0] pins that are inputs to the internal dma controller and is configured by function 3, offset 46h[dmasel].
chapter 4 signal descriptions 51 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.6.16 intirq8# (internal real time clock interrupt) output summary intirq8# is the interrupt from the internal real time clock of the AMD-756 peripheral bus controller. intirq8# is available in the fon, c2, c3, and pos power states and not available in the soff or moff states. this pin can also be configured as gpio16 by the i/o mapped register (base pointer: function 3, offset 58h), offset d0h. 4.6.17 sqwave (square wave clock) output summary sqwave and intirq8# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset d0h. the frequency of sqwave is specified by function 3, offset 4eh. 4.6.18 pcistop# (pci bus clock stop) output summary pcistop# is connected to the system pll clock chip to control the pci bus clock signals. pcistop# can be asserted in the c2, c3, or pos states if enabled by function 3, offset 50h. this pin can also be configured as gpio7 by the i/o mapped register (base pointer: function 3, offset 58h), offset c7h. 4.6.19 pnpirq0 (plug and play interrupt request 0) input summary pnpirq0 and pcistop# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset c7h. pnpirq0 can be assigned to control any of the 12 internal isa irq signals and is configured by function 3, offset 44h.
52 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.6.20 pme# (power management interrupt) input summary pme# is used to generate smi or sci interrupts and resume events. 4.6.21 pwrbtn# (power button) input summary when the system is in the soff state, this signal controls the automatic transition to fon. pwrbtn# can be programmed to generate sci or smi interrupts from any state other than soff. if asserted for four seconds from any state other than soff, a power button override event is generated. a power button override event causes the pwron# pin to be driven high and the i/o mapped register (base pointer: function 3, offset 58h), offset 00h[pbor_sts] to be set high. this pin has a 16-msec debounce when enabled by function 3, offset 41h[pbdebnc]. 4.6.22 pwrgd (power good) input summary pwrgd is connected to the powergood signal on the power supply. this is the reset source for the AMD-756 peripheral bus controller when pwron# is asserted and the system transitions from soff to fon. when inactive, the cpurst#, pcirst#, and rstdrv pins are driven active. after this signal becomes active, at least 1 msec after power and the pciclk input are stable, the logic sequences the release of the reset outputs.
chapter 4 signal descriptions 53 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.6.23 pwron# (main power on) output summary pwron# is the output to the power supply that is used to control the main power sources to the system board, including the vdd3 plane of the AMD-756 peripheral bus controller. this pin is low during the fon, c2, c3, and pos states and high during the soff state. when power is applied to the vdd_soft plane, this signal is reset by the real time clock logic. 4.6.24 ri# (ring indicator) input summary ri# can be connected to external modem circuitry to allow the system to be reactivated by a received phone call. ri# causes the system to resume to the fon state and generates sci or smi interrupts. ri# operation is reflected in register bits the i/o mapped register (base pointer: function 3, offset 58h), offset 16h[ri_rsm], 22h[ri_en], 26h[ri_ctl], 28h[ri_sts], and 2ah[rismi_en]. this pin can also be configured as gpio14 by the i/o mapped register (base pointer: function 3, offset 58h), offset ceh. 4.6.25 serirq (serial irq) bidirectional summary this pin supports the vesa serial-irq protocol. serirq is controlled by function 3, offset 4ah. this pin can also be configured as gpio17 by the i/o mapped register (base pointer: function 3, offset 58h), offset d1h. 4.6.26 msirq (mouse interrupt request) output summary msirq and serirq share the same pin and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset d1h. this signal is the mouse irq from the keyboard controller that normally connects to the pic irq12.
54 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.6.27 smbalert# (smbus alert) input summary smbalert# and irq12 share the same pin, and are selected by function 3, offset 46h[10:9]. when enabled, smbalert# can be used to generate an smi or sci interrupt associated with the smbus logic. sampled smbalert# is sampled at the rising edge of bclk. 4.6.28 smbusc (system management bus clock) bidirectional summary smbusc is the system management bus (smbus) clock. this pin can also be configured as gpio0 by the i/o mapped register (base pointer: function 3, offset 58h), offset c0h. 4.6.29 smbusd (system management bus data) bidirectional summary smbusd is the system management bus (smbus) data. this pin can also be configured as gpio1 by the i/o mapped register (base pointer: function 3, offset 58h), offset c1h. 4.6.30 slpbtn# (sleep button) input summary slpbtn# causes the system to transition between the pos and fon states. if slpbtn# is asserted, the i/o mapped register (base pointer: function 3, offset 58h), offset 00h[slpbtn_sts] is set. enabling slpbtn# by the i/o mapped register (base pointer: function 3, offset 58h), offset 02h[pwrbtn_en] causes an smi or sci interrupt. if the i/o mapped register (base pointer: function 3, offset 58h), offset 26h[slpbtn_ctl] bit is set, this pin transitions the system from soff to fon. this pin can also be configured as gpio3 by the i/o mapped register (base pointer: function 3, offset 58h) offset c3h.
chapter 4 signal descriptions 55 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.6.31 extirq8# (real time clock interrupt) input summary extirq8# and slpbtn# share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset c3h. if an external real time clock is used, this signal can be used as the irq8# input from that source. extirq8# can also wake the system from soff, c2, c3, and pos. if selected, extirq8# originates directly from the pad, not from the gpio input path. 4.6.32 suspend# (processor suspend) output summary this signal is activated during the pos state to control the external power planes. this pin can also be configured as gpio4 by the i/o mapped register (base pointer: function 3, offset 58h), offset c4h. 4.6.33 therm# (thermal warning detect) input summary if enabled by function 3, offset 50h[tth_en], this signal automatically enables throttling as specified by function 3, offset 50h[tth_ratio]. this pin can also be configured as gpio2 by the i/o mapped register (base pointer: function 3, offset 58h), offset c2h.
56 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.7 universal serial bus interface 4.7.1 usbclk (universal serial bus clock) input summary a 48 mhz clock provides timing for both the full speed (12 mbps) and low speed (1.5 mbps) operation. 4.7.2 usbp[3:0] (usb port [3:0] data positive) bidirectional summary usbp[3:0] are the positive signals to differential output drivers that drive the usb port [3:0] data signals on to the usb cable. they support both the full speed (12 mbps) and low speed (1.5 mbps) data rates. 4.7.3 usbn[3:0] (usb port [3:0] data negative) bidirectional summary usbn[3:0] are the negative signals to differential output drivers that drive the usb port[3:0] data signals on to the usb cable. they support both the full speed (12 mbps) and low speed (1.5 mbps_ data rates. 4.7.4 usboc0# (usb over-current detect 0) input summary input. usboc0# is used to monitor the usb power over- current. sampled usboc0# is sampled at the rising edge of bclk.
chapter 4 signal descriptions 57 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.7.5 usboc1# (usb over-current detect 1) input summary usboc1# and irq12 share the same pin, and are selected by function 3, offset 46h[10:9]. when enabled, it can be routed to be a second source of usb port over-current detection. sampled usboc1# is sampled at the rising edge of bclk.
58 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.8 keyboard interface 4.8.1 kbck (keyboard clock) input summary when the internal keyboard controller is enabled, this pin functions as the clock to the keyboard interface. 4.8.2 ka20g (keyboard gate a20) input summary ka20g and kbck share the same pin, and are selected by function 3, offset 48h[intkbc]. the gate a20 function from an external keyboard is summed with the other sources of gate a20 before being passed directly to the processor via a20m#. this pin is a direct connection to a20m# on the processor. 4.8.3 kbdt (keyboard data) output summary kbdt functions as the data line to the keyboard interface. 4.8.4 kbrc# (keyboard reset) input summary kbrc# and kbdt share the same pin, and are selected by function 3, offset 48h [intkbc]. kbrc# functions as a reset input from the external keyboard controller that is used to generate a pulse on cpurst# or init[1:0]#.
chapter 4 signal descriptions 59 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.8.5 keylock (keyboard lock) input summary keylock is the keyboard lock signal for the internal keyboard controller. this pin can be configured as gpio13 by the i/o mapped register (base pointer: function 3, offset 58h), offset cdh. 4.8.6 dbrdy (debug ready) input summary dbrdy and keylock share the same pin, and are selected by the i/o mapped register (base pointer: function 3, offset 58h), offset cdh. when this signal is active, the AMD-756 peripheral bus controller halts the timers specified by function 3, offset 4ch. this allows the processor to execute debugging and performance-monitoring code while the rest of the system is halted. 4.8.7 msck (mouse clock) output summary msck is the mouse clock to the legacy mouse connector. 4.8.8 msdt (mouse data) bidirectional summary msdt is the mouse data to the legacy mouse connector. 4.8.9 ekirq1 (external keyboard controller irq1) output summary ekirq1 and msck share the same pin, and are selected by function 3, offset 48h[intkbc]. this signal sends the external keyboard controller irq1 state to the internal interrupt controller logic.
60 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.8.10 ekirq12 (external keyboard controller irq12) output summary ekirq12 and msdt share the same pin, and are selected by function 3, offset 48h[intkbc]. this signal is the external keyboard controller irq12 sent to the internal interrupt controller logic. refer to function 3, offset 46h[10:9] for information on how the irq12 pin and the mouse interrupt are combined.
chapter 4 signal descriptions 61 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4.9 internal real-time clock 4.9.1 rtcx_in (crystal/oscillator input) input summary rtcx_in is the 32.768-khz crystal input. this pin can be driven by a cmos driver or connected through a crystal oscillator to rtcx_out. note: whether an internal or external real-time clock is selected, this pin is required to provide the 32-khz clock to the AMD-756 peripheral bus controller. 4.9.2 rtcx_out (crystal/oscillator output) output summary rtcx_out is the 32.768-khz crystal output.
62 signal descriptions chapter 4 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4.10 power and ground 4.10.1 gnd (power ground) 4.10.2 gnd_usb (usb differential output ground) 4.10.3 v dd3 (power supply for the processor i/o voltage) this pin should be connected to the same voltage as the processor i/o circuitry. 4.10.4 v dd_ref (power reference) 4.10.5 v dd_rtc (power supply to rtc) this supply is connected to the real time clock. 4.10.6 v dd -soft (power supply) v dd -soft is always available unless the mechanical switch of the power supply is turned off. 4.10.7 v dd -usb (usb differential output power)
chapter 5 functional operations 63 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5 functional operations 5.1 pci bus-initiated accesses the AMD-756 peripheral bus controller is responsible for decoding pci bus requests from pci bus masters, initiating the requested actions, and responding as required by the pci bus protocol. 5.1.1 overview the AMD-756 responds to pci bus cycles by positive decoding or subtractive decoding as defined in the pci specification. the length of the time for both positive and subtractive decoding is fixed at medium decoding. the AMD-756 controller also generates an isa bus cycle for any memory or i/o cycle claimed by the isa function. 5.2 pci bus commands the AMD-756 responds to the pci bus commands as described in the following sections. 5.2.1 interrupt acknowledge the AMD-756 controller releases an 8-bit interrupt vector on ad[7:0] in response to an interrupt acknowledge cycle. 5.2.2 special bus cycles the AMD-756 controller ignores all but two pci special bus cycles. when the AMD-756 decodes a shutdown (0000_0000h during the address phase) the controller will assert init to the processors. in response to a stop-grant (0012_0002h during the
64 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information address phase) the controller receives and enters the appropriate power state. the AMD-756 can then assert dcstop to the amd-751 system controller to signal that it should deassert cke to the sdrams and stop its internal clocks. 5.2.3 i/o read and write all i/o accesses not claimed by other pci targets through asserting devsel# are passed to the isa bus controller and executed as standard isa bus cycles. the AMD-756 steers the data among the pci ad bus and the isa sd bus or the ide data bus, as required by the cycle type. if the access is to an on-chip i/o location, then the data is steered among the ad bus, the sd bus, and the selected internal location, as required by the cycle type. the AMD-756 controller asserts trdy# when all isa bus accesses are completed. in the case of i/o reads, valid data is placed on the pci ad bus before trdy# is asserted. the timing of a pci cycle forwarded to the isa bus is shown in figure 6 on page 67. an 8-bit cycle is four wait states long while a 16-bit cycle has no wait states if the default configuration is used. additional wait states can be inserted by setting bit 5 or bit 4 of the isa bus control register, or by negating iochrdy. figure 4 on page 65 illustrates i/o accesses for both read and write, including the insertion of wait states.
chapter 5 functional operations 65 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 4. i/o access for 32-bit or 24-bit accesses to 16-bit isa bus targets, or for 32-bit, 24-bit, or 16-bit accesses to 8-bit isa bus targets, the AMD-756 controller generates multiple isa bus cycles for each pci bus cycle in order to match the size of the access requested by the pci initiator. requests for non-contiguous bytes are handled by converting the access to the appropriate isa bus cycles. converting a single pci cycle to multiple isa cycles is invisible to the pci interface, except for the increased latency required to complete the operation. the AMD-756 converts a cpu request for 16-bit data from an 8-bit peripheral into two 8-bit cycles as depicted in figure 5 on page 66. 8-bit operation 16-bit operation bclk bale la[23:17] sa[19:0] ior#, iow# iocs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
66 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 5. i/o cycle 16-bit to 8-bit conversion the slot address lines sa1, sa0, and sbhe# function the same for i/o reads and writes as they do for memory reads and writes. 5.2.4 memory read and write the AMD-756 controller directs all memory accesses not claimed by other targets to the isa bus. the AMD-756 steers data between the pci ad bus and the isa data bus as required by the requested cycle. the AMD-756 supports bursting (multiple read or write transactions). if frame# and irdy# are asserted at the same time, the AMD-756 will not disconnect if it is able to complete even byte odd byte bclk bale la[23:17] sa19-sa0 ior#, iow# sa0 sbhe# iocs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
chapter 5 functional operations 67 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the data phase within specified latency requirements. target latency is limited to 16 pci clocks from the assertion of frame# for initial accesses, and limited to eight pci clocks from the end of the previous data phase for subsequent accesses of a burst cycle. all non-posted isa writes and all isa reads use delayed transactions to meet these latency requirements. figure 6 shows the timing of a non-posted pci cycle forwarded to the isa bus. figure 6. non-posted pci-to-isa access if the AMD-756 controller is unable to complete the initial data phase within the required initial latency, it begins a delayed transaction and terminates with retry by asserting stop# but not asserting trdy# at the end of the initial data phase. if the next data phase in a burst cannot be completed within the required incremental latency, the AMD-756 disconnects by asserting trdy# and stop# at the end of the current data phase. memory write posting in the AMD-756 controller is enabled by setting the post memory write enable bit, configuration register function 0, offset 46h, bit 0 (see page 200). when write posting is enabled, trdy# is asserted one clock cycle after both frame# and irdy# are sampled asserted. the AMD-756 pclk sysclk frame# irdy# trdy# stop# ad[31:0] (read) ad[31:1] (write) bale cmd
68 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information completes the access on the isa bus. attempts to access the isa bus before the posted write is complete must wait for the isa bus cycle to complete. the timing for a posted write cycle is shown in figure 7. figure 7. posted pci-to-memory write the memory-related isa bus control signals are memr#, smemr#, memw#, smemw#, and memcs16#. smemr# and smemw# are asserted only if the access is within the first mbyte of memory. the state of memcs16# at the beginning of bus cycle state tc determines whether the present cycle is 8-bit or 16-bit, as shown in figure 8 on page 69. pclk bclk frame# irdy# trdy# stop ad[31:1] (write) bale memw# pclk
chapter 5 functional operations 69 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 8. isa bus memory access cycle the command signals become asserted at the start of tc for 16-bit cycles, or in the middle of tc for 8-bit cycles. the falling edge of a command signal can be delayed by one or two bclks by setting bit 7 of the isa bus control register, function 0, offset 40h (see page page 198). to delay the rising edge of command signals by one bclk set bit 5 in the isa bus control register, function 0, offset 40h. for slow peripherals, wait states may be inserted by negating iochrdy. the AMD-756 converts a pci bus master request for 16-bit, 24-bit, or 32-bit data from an 8-bit isa memory into two, three, or four 8-bit cycles, respectively. a request for 32 bits from a 16-bit isa target results in two 16-bit accesses. the AMD-756 also converts requests for non-contiguous bytes by converting the access to the appropriate isa bus cycles. these conversion cycles are shown in figures 9, 10, and 11. 8-bit operation 16-bit operation bclk bale la[23:17] sa[19:0] memr#, memw# s memr#, smemw# memcs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
70 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 9. isa bus memory cycle: 16-bit to 8-bit conversion even byte odd byte bclk bale la[23:17] sa[19:0] memr#, memw# s memr#, smemw# sa0 sbhe# memcs16# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
chapter 5 functional operations 71 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 10. memory cycle 32-bit to 8-bit conversion bclk bale la[23:17] sa[16:0] memr#, memw# m emr#, smemw# sa1 sa0 sbhe# memcs163 iochrdy sd[15:8] (read) sd[15:8] (write) bclk byte 3 operation byte 0 operation byte 1 operation byte 2 operation
72 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 11. memory cycle 32-bit to 16-bit conversion if the memory accessed is rom, the timing is different for command signals memr# and smemr#, which are asserted at the falling edge of bale. both 8-bit and 16-bit rom access cycles are three wait states long. they can be programmed to be zero or one wait states using bit 1 of the isa bus controller configuration register (see page 198). figure 12 on page 73 shows a rom access. figure 13 on page 74 shows requests for 32 bits of data from 8-bit roms. be=0000 be=1001 bclk bale la[23:17] sa[16:0] memr#, memw# s memr#, smemw# sa1 sa0 sbhe# memcs16# iochrdy sd[15:8] (read) sd[15:8] (write) byte 2 oper byte 1 oper byte 2,3 oper bclk byte 0,1 oper
chapter 5 functional operations 73 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 12. rom access 8-bit read 16-bit read bclk bale la[23:17] sa[16:0] memr#, memw# s memr#, smemw# sa0 sbhe# iochrdy sd[15:8] (read) sd[15:8] (write) bclk
74 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 13. rom cycle 32-bit to 8-bit conversion sa1, sbhe#, and sa0 contain a direct decode of the c/be[3:0]# inputs from the pci bus. during a conversion cycle, sbhe# and sa0 are toggled so that the appropriate bytes are accessed, as shown in table 3. bclk bale la[23:17] sa[16:0] memr#,memw# sa1 sa0 sbhe# memcs16# iochrdy sd15-sd8 read sd15-sd8 write byte 0 operation byte 1 operation byte 2 operation byte 3 operation bclk bclk bclk table 3. isa byte and word accesses sbhe# sa0 description 0016-bit 108-bit, lsb 018-bit, msb 1 1 undefined
chapter 5 functional operations 75 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.2.5 configuration read and write as a target, the AMD-756 controller responds to both read and write configuration cycles when device selection decoding is done externally via the idsel pin. the AMD-756 idsel connection is system-specific, but the recommended connection is to ad18. if the AMD-756 is selected during a pci master-initiated configuration cycle, devsel# is asserted two clocks after frame# assertion. on pci-to-configuration register reads, the AMD-756 controller drives the requested configuration register data onto ad[31:0], asserts trdy# four clocks after frame# is asserted, and negates trdy# and devsel# one clock after irdy# is asserted. on pci-to-configuration register writes, the AMD-756 asserts trdy# four clocks after frame# is asserted or two clocks after irdy# is asserted, whichever is later. data is strobed into the configuration registers the cycle before trdy# is asserted. the timing of these cycles is shown in figure 14 and figure 15. figure 14. configuration read cycle address data cfg-rd be ? s pclk frame# ad idsel c/be[3:0]# irdy# trdy# stop devsel# pclk
76 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 15. configuration write cycle 5.2.6 memory read multiple the memory read multiple command is treated the same as a memory read command by the AMD-756 controller. 5.2.7 dual address line the AMD-756 supports 32-bit addressing only, so dual address line commands are ignored. there is no response. 5.2.8 memory read line the AMD-756 controller treats the memory read line command just as it does the memory read command. 5.2.9 memory write invalidate the AMD-756 treats the memory write invalidate command just as it does the memory write command. address data-in cfg-wr be ? s pclk frame# ad idsel c/be[3:0]# irdy# trdy# stop devsel# pclk
chapter 5 functional operations 77 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.3 pci bus features 5.3.1 back-to-back cycles as a target, the AMD-756 controller can respond to fast back-to-back cycles as described in the pci specification. all back-to-back cycles by the same initiator require at least one turn-around cycle, except when both transactions are writes to the same target. 5.3.2 subtractive decoding subtractive decoding ensures that every pci bus access gets a response. any pci cycle not claimed by other targets and whose address is not defined in the AMD-756 controller address block is forwarded to the isa bus. the timing for subtractive decoding is shown in figure 16. figure 16. subtractive decode timing 5.3.3 isa bus control register bus control options can be programmed via the isa bus control register, function 0, offset 40h (see page 198). this register controls the number of wait states to be inserted in the 8-bit and 16-bit slot cycles and determines the output drive of the slot bus buffers. more than five wait states are possible if iochrdy is pulled low before the last normal wait state. 12 3 4 5 6 7 fast med slow sub pclk frame# irdy# trdy# devsel#
78 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.4 isa bus-initiated cycles the AMD-756 controller is responsible for forwarding isa bus cycles to the pci bus. the only two initiators on the isa bus are the dma controller and the isa bus master. the dma controller can only generate memory read and write cycles, while an isa master can generate i/o as well as memory cycles. masters must repeat a read or write transaction that is terminated with retry. masters must assert irdy# within eight clocks during all data phases. ideally, irdy# is asserted with no delay on all data phases. 5.4.1 dma-initiated cycles in the pc/at, dma transfers occur between peripherals and memory with a data width of either 8 or 16 bits. of the seven external dma channels available, four are used for 8-bit transfers and three for 16-bit transfers. one byte or word is transferred in each dma cycle. normally, an add-on card issues a dma request by asserting one of the drq[7:5] or drq[3:0] signals. when the AMD-756 detects this request and the request is a read from memory, it generates a request to the pci arbiter. when it receives a pci grant, the AMD-756 controller initiates a pci memory read transaction using the current dma address, prefetching all data within the addressed doubleword. when the transaction is complete, the AMD-756 asserts the corresponding dack# line to indicate a dma acknowledge. prefetch data is transferred in response to subsequent dma requests without further pci bus accesses. when the AMD-756 controller detects a memory write request, it asserts the corresponding dack# line to indicate the dma acknowledge, reads the data from the dma device, and merges the data into a single doubleword. when the last byte of the doubleword has been read, the AMD-756 generates a request to the pci arbiter. when it receives a pci grant, it starts a pci memory write transaction for the entire doubleword with appropriate byte enables.
chapter 5 functional operations 79 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information aen and bale are asserted after the dma is acknowledged and any pending isa bus cycle has completed. the dma address is placed on la[23:20] and sa[16:0]. two dmaclk cycles later, either memr# and iow# or memw# and ior# are asserted, depending on the direction of the transfer. if the isa command delay bit of the isa bus control register is set, memr# is asserted one dmaclk cycle earlier. the command remains asserted for three dmaclk cycles. the data transfer takes place on the rising edges of command signals. tc is activated before the end of the command if the transfer is from one 8-bit device to another or one 16-bit device to another. if the transfer is from a 16-bit device to an 8-bit device, the command signals are again asserted after a delay of two dmaclk cycles and the transfer is complete. figure 17 on page 80 shows the timing for a typical dma transfer. due to concurrent pci and isa bus operation during dma, the timing on each bus is independent of the state of the other bus. the state of the data buffers determines when pci bus requests are generated and when dma wait states are generated by negating iochrdy. pci bus requests to the arbiter during memory reads are issued only when the memory read buffer is empty. during memory writes, pci bus requests are issued when the msb of the memory write buffer is full. iochrdy is negated when the memory read buffer is empty during memory reads, or when the memory write buffer is full during memory writes.
80 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 17. dma transfer cycle 5.4.2 isa bus master initiated cycles an isa bus master card issues a dma request on the isa bus, as shown in figure 18 on page 81, using a dma channel which has been placed in the cascade mode. the AMD-756 controller responds with an acknowledge signal in the same manner as for a dma cycle. the add-on card then gains control of the isa bus by asserting the master# signal. unlike dma cycles, there can be multiple data transfers in master mode. an isa bus master can generate both memory and i/o accesses. bclk dclk (internal) drq[3:0] hold (internal) hlda (internal) bale, aen dack[7:5]#, la[23:17] sa[15:8] sa[7:2] sa[1:0] ior#, memr# memw#/iow# tc smemw# bclk dclk (internal) bclk dclk (internal) dack[3:0]#
chapter 5 functional operations 81 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 18. isa bus master arbitration timing when the AMD-756 controller detects memr# or memw# asserted, it starts the pci cycle, asserts frame#, and negates iochrdy. this procedure guarantees that the isa cycle will not complete before the pci cycle has provided or accepted the data. iochrdy is asserted when irdy# and trdy# are sampled asserted. figure 19 on page 82 shows an isa bus master memory read, and figure 20 on page 82 shows a isa bus master memory write. the isa bus and pci bus operate concurrently. a separate pci bus request is issued for each isa master command and the pci bus ownership is relinquished after the transaction is completed. the AMD-756 converts isa bus master i/o cycles into pci i/o cycles. the timing of these cycles is similar to that of the memory cycles shown in figure 17 on page 80 and figure 18 on page 81, with the substitution of ior# and iow# for memr# and memw#. bclk dclk (internal) drq[7:5], drq[3:0] dack[7:5]#, dack[3:0]# master# aen bclk
82 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 19. isa bus master-to-pci memory (memory read) figure 20. isa bus master-to-pci memory (memory write) pclk bclk memr# sd[15:0] iochrdy frame# ad[31:0] (read) irdy# trdy# pclk pclk pclk pclk bclk memr# sd[15:0] iochrdy frame# ad31-ad0(read) irdy# trdy# pclk
chapter 5 functional operations 83 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.5 pci bus arbitration the signals preq# and pgnt# are used to control requests for and grants of the pci bus between the AMD-756 peripheral bus controller and the amd-751 system controller. 5.6 i/o and memory mapping the AMD-756 decodes pci bus addresses to determine the destination of a pci memory or i/o request. the AMD-756 address decoder distinguishes five regions for memory or i/o accesses. the regions are: n ide bus i/o n bus master ide register i/o n isa bus i/o (on-chip) n isa bus i/o (off-chip) n isa bus off-board memory the region selected is a function of the pci address, the pci cycle type, and the values placed in the configuration registers that control memory mapping. the regions are described below. ide bus i/o location the AMD-756 controller generates an ide bus access cycle via positive decoding and responds to the cycle when it recognizes an ide target address. bus master ide register i/o location an internal i/o access cycle is generated via positive decoding to the appropriate bus master ide register i/o block, and is responded to by the AMD-756 when it recognizes a bus master ide register target address. the base address of the bus master ide registers is set by the configuration base registers and the size is fixed at 16 bytes (8 bytes for each channel). isa bus i/o location (on-chip) the AMD-756 controller generates an isa bus i/o access cycle by subtractive decoding and is responded to by the AMD-756 when it recognizes an on-chip address during the isa bus cycle. isa bus i/o location (off-chip) the AMD-756 generates a standard isa bus i/o access cycle by subtractive decoding when no other pci target responds to a
84 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information pci i/o cycle. data is passed between the pci data bus (ad[31:0]) and the isa data bus (sd[15:0]). rom_kbcs# is asserted to select the keyboard controller if the i/o address is port 60h or port 64h. isa bus off-board memory location standard 8-bit or 16-bit isa bus cycles are generated when the AMD-756 controller detects a memory access in the isa slot bus address range. data is passed between the pci data bus (ad[31:0]) and the isa data bus (sd[15:0]). the AMD-756 determines off-board memory locations through subtractive decoding of a pci-to-isa access (when none of the other targets asserts devsel#). if the isa address is defined as a rom region, rom_kbcs# is asserted. 5.6.1 i/o mapping i/o addresses not inhibited by devsel# are run as isa bus cycles. the data steering is based on the actual i/o addresses, depending on whether the i/o location is on-chip or off-chip. on-chip i/o for on-chip centralized and distributed dma devices, the isa bus cycle is run normally. only the steering on read cycles is affected. isa bus masters have access to all on-chip registers. the centralized dma i/o locations are at a fixed address, as shown in table 4, while the distributed dma i/o locations are at programmable base addresses. table 4. i/o fixed address mapping address device location 0000h ? 000fh dma#1 on-chip or pci bus 0080h ? 008fh dma page registers on-chip 00c0h ? 00dfh dma#2 on-chip or pci bus 0170h ? 0177h ide channel 2 ide bus 01f0h ? 01f7h ide channel 1 ide bus 0376h ide channel 2 ide bus 03f6h ide channel 1 ide bus 0010h ? 007fh, 0090h ? 00bfh, 00e0h ? 016fh, 0178h ? 01efh, 01f8h ? 0375h, 0378h ? 03f5h, 03f8h ? ffffh general i/o locations pci/isa bus
chapter 5 functional operations 85 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information sa bus i/o all i/o write cycles drive the data from the ad bus onto the sd bus and generate an iow# strobe. all i/o read cycles drive data from the sd bus onto the ad bus and generate an ior# strobe. the AMD-756 controller drives data onto the sd bus during all on-chip reads, while the sd bus is the data source for all other i/o reads. 5.6.2 memory mapping memory accesses are divided into pci memory, rom, and isa bus memory accesses. table 5 shows the various memory regions and the destinations (pci, rom, or isa) supported by the AMD-756. when a pci memory access is generated, one of the following events will occur. n if the devsel# input is sampled asserted within the fast, medium, or slow sample periods, the AMD-756 controller is deselected and a pci target device completes the cycle. table 5. memory address mapping range address destination comments 0 to 786 kbytes 0_0000h ? b_ffffh pci bus space isa bus space selected by asserted devsel# (by subtractive decode) 786kbytes to 960kbytes c_0000h ? e_ffffh pci bus space isa bus space isa rom space selected by asserted devsel# (by subtractive decode) or selected by rom decode control 960kbytes to 1 mbyte f_0000h ? f_ffffh isa bus space isa rom space (by subtractive decode) 1 mbyte to 15.875 mbytes 10_0000h ? fd_ffffh pci bus space isa bus space selected by asserted devsel# (by subtractive decode) 15.875 mbytes to 16 mbytes fe_0000h ? ff_ffffh pci bus space isa bus space selected by asserted devsel# (by subtractive decode) 16 mbytes t0 128 mbytes 100_0000h ? 7ff_ffffh pci bus space aliased isa bus space selected by asserted devsel# (by subtractive decode) 128 mbytes to (4 gbytes ? 512 kbytes) 8000_0000h ? fff7_ffffh pci bus space aliased isa bus space selected by asserted devsel# by subtractive decode only (4gbytes ? 512kby tes) to 4 gbytes fff8_0000h ? ffff_ffffh isa rom space (by subtractive decode) or selected by rom decode control
86 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information n if the devsel# input is not sampled asserted within the fast, medium, or slow sample periods, the AMD-756 executes a subtractive decode which directs the access to the isa bus. when a master mode or dma isa memory access is generated, the AMD-756 controller initiates a pci cycle. if devsel# is not asserted within the fast, medium, or slow sample periods, the AMD-756 executes a subtractive decode which directs the access to the isa bus, and iochrdy is re-asserted to allow the isa cycle to complete. isa memory all memory accesses at or below ff_ffffh (16 mbytes) that are not accepted by pci bus devices through the assertion of devsel# are directed to the isa bus. the AMD-756 controller asserts devsel# for the cycles and generates standard isa cycles. it also provides the data latching and steering logic to allow the pci initiator to perform 8-bit, 16-bit, 24-bit, or 32-bit accesses to either 8-bit or 16-bit isa memory devices. accesses to the pci bus performed subtractively above ff_ffffh (16 mbytes) are aliased to the 24-bit isa bus addresses. pci accesses to these regions are performed only if no dma or master mode cycles ever access the referenced locations, because a slot bus memory device might occupy the same aliased address as a pci bus memory device, causing bus contention. access to system rom is provided in the top 512 kbytes of the aliased isa bus address space for correct reset vectoring. 5.6.3 system rom memory mapping setting bits in the rom decode control enable different address ranges to be included in the romcs# decode. pci accesses to the highest 512 kbytes of each 16 mbyte memory space (xxf8_0000h to xxff_ffffh) are system rom accesses. system rom accesses are a subset of isa bus accesses, and are generated as standard isa bus accesses, except that: n romcs# is always asserted n additional isa bus wait states can be programmed via the rom wait states bit of the isa bus control register.
chapter 5 functional operations 87 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the AMD-756 controller provides data latching and steering logic to allow the initiators to perform 8-bit, 16-bit, 24-bit, or 32-bit accesses to 8-bit system roms. it also performs the required isa bus cycles to assemble and latch the appropriate data and to present it to the pci initiator as requested. system rom is also accessible by isa bus masters and dma cycles. video rom and fixed disk rom, memory range c0000h to cffffh, can be defined to be in the system rom range using bits 7 ? 0 of the rom decode control register (function 0, offset 43h). the programmable values of these bits are shown in table 6. setting the indicated bit enables the address range shown to be included in the romcs# decode. subtractive decodes are always performed, and the rom access may be inhibited by a pci target that is asserting devsel# and claiming the cycle. flash memory support support for programmable flash memory is provided by enabling write cycles to the bios rom regions. bit 0 of the isa bus control register (function 0 offset 40h) is provided to enable write cycle generation. table 6. rom decode control register bit value address range enabled bit 7 = 1 fffe 0000h ? fffeffffh enabled bit 6 = 1 fff80000h ? fffdffffh enabled bit 5 = 1 000e8000h ? 000effffh enabled bit 4 = 1 000e0000h ? 000e7fffh enabled bit 3 = 1 000d8000h ? 000d ffffh enabled bit 2 = 1 000d0000h ? 000d7fffh enabled bit 1 = 1 000c8000h ? 000c ffffh enabled bit 0 = 1 000c0000h ? 000c7fffh enabled
88 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.7 power planes and reset the AMD-756 controller has six power planes listed in table 7. in addition to these six power planes, there is a single ground plane called gnd. note: the operational tolerance on vdd3, vdd_soft, vdd_usb, and vdd_rtc is from 3.0 to 3.6 volts. 5.8 clock generation the clocks described in the following paragraphs are used or generated by the AMD-756. pclk this input signal is the pci clock used to synchronize the interface to all pci bus devices. pclk can operates frequencies up to 33.333mhz. osc this input signal is a 14.318-mhz clock common to the isa bus signal osc and is used by the programmable interval timer (pit), by some of the power management logic, and to optionally create bclk. table 7. AMD-756? peripheral bus controller power planes name # of pins description vdd3 11 main source of 3.3 volts in the ic core and i/o cells. this plane is powered down when the pwron# output (to the power supply) is in the negated state. this plane powers all pins not powered by vdd_soft, vdd_usb, and vdd_rtc. vdd_soft 1 sleep-mode 3.3-volt power. when most of the system is powered down (pwron# is in the negated state), this plain remains powered. this plane is used to detect wake events. the pins powered by this plane are pwrbtn#, pwron#, pme#, smbus[c,d], extsmi#, slpbtn#, ri#, and pwrgd. vdd_ref 1 reference voltage for 5-volt tolerant i/o cells. in 3.3-volt system (where 5-volt tolerance is not necessary), this plane should be tied to the 3.3-volt supply. this pin should be connected to the 5-volt output of the power supply that is asserted in the soff power state (soft off) ? the 5-volt version of vdd_soft from the power supply enters this pin and is regulated down to 3.3 volts to drive the vdd_soft pin. vdd_usb and gnd_usb 1 each usb differential output power source. these are used to power the usb transceivers. the pins powered by this plane are usbp[3:0] and usbn[3:0]. vdd_rtc 1 battery power for the real-time clock. this plane is normally always powered. the pins powered by this plane are rtcx_in and rtcx_out.
chapter 5 functional operations 89 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information usbclk this input 48-mhz clock is used by the usb controller. kbck this clock is the output clock to the keyboard when the internal keyboard controller is selected msk this clock is the output clock to the mouse when the internal keyboard controller is selected. rtc_xin, rtc_xout the clock generated by this oscillator is a 32.768-khz oscillator pair and is used by the real-time clock. this clock is powered by the vdd_rtc power plane. picclk this clock is the apic interrupt message bus clock. this is used as the clock for the programmable frequency clock for interrupt message bus. the frequency is specified by function 0, offset 4b bits [apiccks]. bclk this output signal is the isa bus system clock. it is derived either by a division of pclk by 2, 3, 4, 5, 6, 10, or 12, or by a division of osc by 2. bclk timing is controlled by programming the isa clock control register, function 0, offset 42h. bit 3 of this register, the isa clock select enable bit, is cleared at reset, forcing bclk to default to a value of = pclk/4. to program a different time value for bclk, take the following steps. 1. clear bit 3 of the isa clock control register. 2. program bits 2 ? 0, the isa bus clock select bits of this register, writing the value selected from table 8. 3. set bit 3 of the isa clock control register. table 8. isa bus clock select bit programming bit 2 bit 1 bit 0 bclk value 0 0 0 pclk / 3 (default) 001pclk / 2 010pclk / 4 011pclk / 6 100pclk / 5 101pclk / 10 110pclk / 12 111osc / 2
90 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.9 resets pwrgd (power good) from the power supply is the main source of reset for the AMD-756 vdd3 logic. from this signal, pcirst#, rstdrv, and cpurst are derived. the normal power-up sequence is shown in figure 21. figure 21. normal power-up sequence a 1.8-msec delay occurs between the start of pwrgd and the end of pcirst# and rstdrv. this delay can be shortened (for simulation and test purposes) by forcing the iochrdy pin low while the pwrgd signal transitions from low to high. if this procedure is followed, the delay from pwrgd to pcirst#/rstdrv is reduced to approximately 1.5 microseconds. the system can be reset by writing a 1 to function 0 offset 47h bit [swpcir]. this resets most of the internal registers and generates a pulse on pcirst#, rstdrv, and cpurst. the pulse generated on pcirst# and rstdrv is four pclk cycles long. at the end of this pulse, cpurst remains asserted for three additional pclk cycles. the system can also be reset via the keyboard controller, port92 (system control register, fixed-address i/o port 92h), and a shutdown command. these all generate pulses that are 1.0 to 1.5 microseconds long. if function 0 offset 47 bit [cpurs] is high, these reset commands generate pulses on the init# pins rather than cpurst. : vdd3 pwrgd pcirst# rstdrv 1.5 us > 100 ms ms = milliseconds; us = microseconds cpurst 1.8 ms
chapter 5 functional operations 91 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.10 direct memory access the dma controllers are 8237-compatible, have internal latches for latching the middle address bits output by the 8237 megacells on the data bus, and have 74ls612 equivalent memory mappers to generate the upper address bits. the dma logic controls transfers between an i/o channel and on-board or off-board memory. this logic generates a bus request to the pci bus when an i/o channel requests a dma operation. once a bus grant has been issued, and any pending access to the isa bus is completed, the dma controller drives the pci address bus and the slot address bus. dma transfers can occur over the full 16 mbyte range available on the slot bus and the entire 32-bit address range of the pci bus. 5.10.1 dma controllers the AMD-756 controller supports seven dma channels using two 8237 equivalent megacells capable of running at bclk. this option is programmable via the type f dma control register (function 0, offset 45h). dma controller 1 contains channels 0 through 3. these channels support 8-bit i/o adapters. they are used to transfer data between 8-bit peripherals and 8-bit or 16-bit memory. each channel can transfer data in 64-kbyte pages within the first 16 mbytes of the pci memory space. dma controller 2 contains channels 4 through 7. channel 4 is used to cascade dma controller 1, so it is not available externally. channels 5 through 7 support 16-bit i/o adapters to transfer data between these adapters and 16-bit system memory. each channel can transfer data in 128-kbyte pages within the first 16 mbytes of the pci memory space. channels 5, 6, and 7 are meant to transfer 16-bit words only and cannot address odd bytes in system memory. 5.10.2 dma controller registers the 8237 megacells can be programmed anytime pgnt# is negated, i.e., when dma controllers are not in operation. table 9 on page 92 lists the i/o addresses of all target and master
92 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information dma controller registers that can be read or written in the 8237 megacells. channels 0 ? 3 of the master and target dma controllers control system dma channels 0 ? 3. there are 16 master and target dma controller registers. target and master dma controllers ports c0h ? dfh the target and master dma controller ports are in table 9. when writing to a channel address or word count register, the data is written into both the base register and current register simultaneously. when reading a channel address or word count register, only the current address or word count can be read. the base address and base word count are not accessible for reading. the address and word count registers for each channel are 16-bit registers. the value on the data bus is written into the upper byte or lower byte, depending on the state of the internal addressing flip-flop. this flip-flop can be cleared by the clear byte pointer flip-flop command. following this command, the first read/write to an address or word count register will read or write to the least significant byte of the 16-bit register and the byte pointer flip-flop toggles back to zero. table 9. ports 00h ? 0fh master dma controller target i/o address bits master i/o address bits register name access 0000 0000 1100 000x 0000 0000 000x 0000 ch 0 base/current address rw 0000 0000 1100 001x 0000 0000 000x 0001 ch 0 base/current count rw 0000 0000 1100 010x 0000 0000 000x 0010 ch 1 base/current address rw 0000 0000 1100 011x 0000 0000 000x 0011 ch 1 base/current count rw 0000 0000 1100 100x 0000 0000 000x 0100 ch 2 base/current address rw 0000 0000 1100 101x 0000 0000 000x 0101 ch 2 base/current count rw 0000 0000 1100 110x 0000 0000 000x 0110 ch 3 base/current address rw 0000 0000 1100 111x 0000 0000 000x 0111 ch 3 base/current count rw 0000 0000 1101 000x 0000 0000 000x 1000 status/command rw 0000 0000 1101 001x 0000 0000 000x 1001 write request wo 0000 0000 1101 010x 0000 0000 000x 1010 write single mask wo 0000 0000 1101 011x 0000 0000 000x 1011 write mode wo 0000 0000 1101 100x 0000 0000 000x 1100 clear byte pointer f/f wo 0000 0000 1101 101x 0000 0000 000x 1101 master clear wo 0000 0000 1101 110x 0000 0000 000x 1110 clear mask wo 0000 0000 1101 111x 0000 0000 000x 1111 r/w all mask bits rw note: not all address bits are decoded.
chapter 5 functional operations 93 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the 8237 dma controller megacells allow the user to program the asserted level of the dreq and dack# signals to be active low or high. because the two megacells are cascaded together internally on the chip, dreq must always be programmed active high and dack# active low. when programming the 16-bit channels (dma controller 2, channels 5, 6, and 7), the address written to the base register must be the real address divided by two. the base word count for these channels is the number of 16-bit words to be transferred, not the number of bytes, as is the case for the 8-bit channels (dma controller 1, channels 0, 1, 2, and 3). it is recommended that all internal locations in the 8237 megacells, especially the mode registers, must be loaded with some valid value, even if the channels are not used. 5.10.3 middle address bit latches the middle dma address bits are held in an internal 8-bit register. the dma controller drives the value to be loaded onto the internal data bus, then issues an address strobe signal to latch the data bus value into this register. an address strobe is issued at the beginning of a dma cycle and any time the lower 8-bit address increments across the 8-bit subpage boundary during block transfers. this register cannot be read or written to externally. it is loaded only from the address strobe signals from the megacells, and the outputs go only to the ad[16:8] pins. 5.10.4 page registers the AMD-756 controller uses two 74ls612 cells to generate the page registers for each dma channel. the page registers provide the upper address bits during dma cycles. dma addresses do not increment or decrement across page boundaries. page boundaries for the 8-bit channels (channels 0, 1, 2, and 3) are every 64 kbytes. page boundaries for the 16-bit channels (channels 5, 6, and 7) are every 128 kbytes. there are 32 8-bit registers between the 612 megacells. page registers must be written at the i/o addresses shown in table 10 to select the correct page for each dma channel before any dma operations are performed. address locations
94 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information between 080h and 08fh other than those shown in the table are not used by the dma channels, but can be read or written to by a pci bus master. the page register is used to set the values for ad[23:16] bus lines. in normal operation, zeroes are driven onto pci address bits ad[31:24] during dma cycles, making the AMD-756 backward-compatible with the pc/at standard. 5.10.5 dma address generation dma addresses are organized as upper, middle, and lower address portions. the upper address portion selects a specific page, and is generated by the page registers in the 74ls612 megacells. the page registers for each channel must be set up by the system before a dma operation. dma addresses do not increment or decrement across page boundaries. page sizes are 64 kbytes for 8-bit channels 0 through 3, and 128 kbytes for 16-bit channels 5 through 7. the dma page register values are output on pci address bus ad[31:16] (8-bit channels) and ad[31:17] (16-bit channels). the middle address portion, which selects a block within the page, is generated by the 8237 megacells at the beginning of a dma operation and any time the dma address increments or decrements through a block boundary. the block size of an 8-bit channel is 256 bytes, while that of a 16-bit channel is 512 bytes. the middle address portion is output by the 8237 megacells onto the internal data bus were it is latched. the table 10. ports 80h ? 8fh dma page register access page register address dma channel i/o address bits 15 ? 0 register name 87h 0 0000 0000 1000 0111 ch 0 dma page m[0] rw 83h 1 0000 0000 1000 0011 ch 1 dma page m[1] rw 81h 2 0000 0000 1000 0001 ch 2 dma page m[2] rw 82h 3 0000 0000 1000 1101 ch 3 dma page m[3] rw 8bh 5 0000 0000 1000 1111 ch 5 dma page m[5] rw 89h 6 0000 0000 1000 1011 ch 6 dma page m[6] rw 8ah 7 0000 0000 1000 1001 ch 7 dma page m[7] rw 8fh 4 0000 0000 1000 1010 ch 4 dma page m[4] rw
chapter 5 functional operations 95 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information latched address are then driven on pci address bits ad[15:8] for 8-bit channels and ad[16:9] for 16-bit channels. the lower address portion is generated directly by the 8237 megacells during dma operations, and the lower address bits are output on pci address bits ad[7:0] for 8-bit channels and ad[8:1] for 16-bit channels. sbhe# is configured as an output during all dma operations it is driven as the inversion of ad0 during 8-bit cycles, and forced low for all 16-bit dma cycles. table 11 shows the mapping from the dma subsystem signals to slot bus signals. table 12 on page 96 shows the mapping of the AMD-756 controller dma subsystem signals to pci address bus signals. table 11. dma addressing for isa bus accesses (dma/slot bus) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits m[7] la[23] la[23] m[6] la[22] la[22] m[5] la[21] la[21] m[4] s/la[20] s/la[20] m[3] s/la[19] s/la[19] m[2] s/la[18] s/la[18] m[1] s/la[17] s/la[17] m[0] s/la[16] ? d[7] s/la[15] s/la[16] d[6] s/la[14] s/la[15] d[5] s/la[13] s/la[14] d[4] s/la[12] s/la[13] d[3] s/la[11] s/la[12] d[2] s/la[10] s/la[11] d[1] s/la[9] s/la[10] d[0] s/la[8] s/la[9] a[7] s/la[7] s/la[8] a[6] s/la[6] s/la[7] a[5] s/la[5] s/la[6] a[4] s/la[4] s/la[5] a[3] s/la[3] s/la[4]
96 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information a[2] s/la[2] s/la[3] a[1] s/la[1] s/la[2] a[0] s/la[0] s/la[1] vss ? s/la[0] a[0]# sbhe# ? vss ? sbhe# table 12. dma addressing for isa bus accesses (dma/pci ad bus) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits 0 ad[31] ad[31] 0 ad[30] ad[30] 0 ad[29] ad[29] 0 ad[28] ad[28] 0 ad[27] ad[27] 0 ad[26] ad[26] 0 ad[25] ad[25] 0 ad[24] ad[24] m[7] ad[23] ad[23] m[6] ad[22] ad[22] m[5] ad[21] ad[21] m[4] ad[20] ad[20] m[3] ad[19] ad[19] m[2] ad[18] ad[18] m[1] ad[17] ad[17] m[0] ad[16] ? d[7] ad[15] ad[16] d[6] ad[14] ad[15] d[5] ad[13] ad[14] d[4] ad[12] ad[13] d[3] ad[11] ad[12] d[2] ad[10] ad[11] d[1] ad[9] ad[10] table 11. dma addressing for isa bus accesses (dma/slot bus) (continued) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits
chapter 5 functional operations 97 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.10.6 type f dma type f dma is supported on all channels. the channels can be individually enabled to provide type f dma timing, using the type f dma control register (function 0, offset 45h) as shown in table 13 on page 97. therefore, configuration software needs to detect type f-capable devices and configure their channels only once after reset. d[0] ad[8] ad[9] a[7] ad[7] ad[8] a[6] ad[6] ad[7] a[5] ad[5] ad[6] a[4] ad[4] ad[5] a[3] ad[3] ad[4] a[2] ad[2] ad[3] a[1] ? ad[2] a[0] ? be[1], be[0] a[0]# ? be[3], be[2] a[1] + a[0] be[0]# ? a[1] + a#[0] be#[1] ? a[1] + a[0] be#[2] ? a#[1] + a#[0] be#[3] ? table 12. dma addressing for isa bus accesses (dma/pci ad bus) (continued) page register outputs middle address latch outputs 8237 address outputs dma1 isa address bits dma2 isa address bits table 13. type f dma control offset 45h type f dma control default bit 7 = 1 isa master/dma to pci line buffer 0 bit 6 = 1 enable dma type f timing on channel 7 0 bit 5 = 1 enable dma type f timing on channel 6 0 bit 4 = 1 enable dma type f timing on channel 5 0 bit 3 = 1 enable dma type f timing on channel 3 0 bit 2 = 1 enable dma type f timing on channel 2 0 bit 1 = 1 enable dma type f timing on channel 1 0 bit 0 = 1 enable dma type f timing on channel 0 0
98 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information when type f dma is enabled for a channel, type f dma transfers occur during the dack# for that channel. that is, the programmed timing parameters are ignored, dma cycles occur with zero wait states, and the dma clock is set equal to bclk. figure 22. type f dma timing 5.10.7 dma channel mapping registers dma channel mapping allows the selection of any dma channel number for each plug-n-play dma request/acknowledge signal pair. the mapping register allows each plug-n-play dma pin pair to be connected to any dma channel. when a plug-n-play dma pin pair is connected to a dma channel, that channel ? s normal isa pin pair is disabled so that the drq is ignored and the dack# is driven high. 5.10.8 ready control logic the ready input to each of the 8237 megacells is driven from the same source within the ready control logic. the AMD-756 controller ready control logic forces the preprogrammed number of wait states on every dma transfer. if needed, the external signal iochrdy goes into the ready control logic to extend transfer signals. to add extra wait states, an external device can pull iochrdy low within the s1 s2 s3 s4 s2 s3 s4 si bclk dclk (internal) drq bale, aen dack[7:5]#, dack[3:0]# ior# tc sd[15:0] bclk
chapter 5 functional operations 99 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information setup time before the second phase of the internal dma clock no later than the last forced wait state cycle. the current dma cycle is then extended by inserting wait states until iochrdy is returned high. iochrdy going high must meet the setup time at the beginning of a wait state or an extra wait state is inserted before the dma controller transitions to state s4. figure 23. dma ready timing 5.10.9 external cascading an external dma controller or bus master can be attached to an at-compatible design through the AMD-756 dma controllers. to add an external dma controller, one of the seven available dma channels must be programmed in the cascade mode. this channel ? s drq signal is then connected to the external dma controller ? s hlda input. when one of the seven channels is programmed in the cascade mode and that channel is acknowledged, the AMD-756 controller does not drive the data bus, the command signals, or the address bus. an external device can become a bus master and control the system address, data, and command buses in much the same manner. to enable this control, one of the external channels must be programmed in the cascade mode. the external device then asserts the drq line for that channel. when the channel ? s dack# line goes asserted, the external device can then pull the master# signal low. as in the dma controller cascading, the AMD-756 does not drive the address, data, and command signals while the cascaded channel ? s dack# signal is asserted. setup dma rdy setup s2 s3 sw s4 si sw bclk dclk (internal) drq dack7-dack5#, ior# iochrdy dack3-dack0#
100 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.11 distributed dma support distributed dma is pci bus mastering with a legacy-compatible programming mode. it offers upward compatibility for isa legacy devices in pci bus systems, providing a vast improvement in performance over previous generation devices. each channel in the 8237 dma controller is mapped to an individual dma slice. the channel 0 base address register, current address, base count and current count, command, status, request etc. are mapped to dma slice dma0. each slice exists in a separate, non-overlapping i/o address space in the pci bus space. the distributed dma control register is located in function 0, offset 60h ? 6fh. each channel base address can be individually programmed and enabled. 5.11.1 target dma channel each target dma channel has a block of sixteen 8-bit registers which are defined in table 14. this block is locatable anywhere in the legacy 64k i/o space by programming the target dma configuration register. all target dma channels must have an identical programming model. the master dma is programmed with the base address of each target dma by having a matching base address register for each channel. table 14. programming model for single target dma channel target address read/ write register name byte dma address word dma address por value b + 0h w base address 0 ? 7 ch0 =0000h ch1 =0002h ch2 =0004h ch3 =0006h ch4 =00c0h ch5 =00c4h ch6 =00c8h ch7 =00cch xxh b + 0h r current address 0 ? 7 ch0 =0000h ch1 =0002h ch2 =0004h ch3 =0006h ch4 =00c0h ch5 =00c4h ch6 =00c8h ch7 =00cch xxh
chapter 5 functional operations 101 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information b + 1h w base address 8 ? 15 ch0 =0000h ch1 =0002h ch2 =0004h ch3 = 0006h ch4 =00c0h ch5 =00c4h ch6 =00c8h ch7 =00cch xxh b + 1h r current address 8 ? 15 ch0 =0000h ch1 =0002h ch2 =0004h ch3 =0006h ch4 =00c0h ch5 =00c4h ch6 =00c8h ch7 =00cch xxh b + 2h w base address 16 ? 23 ch0 =0087h ch1 =0083h ch2 =0081h ch3 =0082h ch4 =n/a ch5 =008bh ch6 =0089h ch7 =008ah xx b + 2h r current address 16 ? 23 ch0 =0087h ch1 =0083h ch2 =0081h ch3 =0082h ch4 =n/a ch5 =008bh ch6 =0089h ch7 = 008ah xxh b + 3h w base address 24 ? 31 n/a n/a b + 3h r current address 24 ? 31 n/a n/a b + 4h w base word count 0 ? 7 ch0 =0001h ch1 =0003h ch2 =0005h ch3 =0007h ch4 =00c2h ch5 =00c6h ch6 =00cah ch7 =00ceh xxh b +4h r current word count 0 ? 7 ch0 =0001h ch1 =0003h ch2 =0005h ch3 =0007h ch4 =00c2h ch5 =00c6h ch6 =00cah ch7 =00ceh xxh b + 5h w base word count 8 ? 15 ch0 =0001h ch1 =0003h ch2 =0005h ch3 =0007h ch4 =00c2h ch5 =00c6h ch6 =00cah ch7 =00ceh xxh b + 5h r current word count 8 ? 15 ch0 =0001h ch1 =0003h ch2 =0005h ch3 =0007h ch4 =00c2h ch5 =00c6h ch6 =00cah ch7 =00ceh xxh b + 6h w base word count 16 ? 23 n/a n/a b + 6h r current word count 16 ? 23 n/a n/a b + 7h n/a reserved (note 1) b + 8h w command 0008h 00d0h 00h b + 8h r status 008h 00d0h x0h b + 9h w request 0009h 00d2h 00h b + ah n/a reserved (note 1) b + bh w mode 000bh 00d6h 00h b + ch w reserved (note 1) table 14. programming model for single target dma channel (continued) target address read/ write register name byte dma address word dma address por value
102 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.11.2 dma control registers there are two physical dma controllers in a legacy pc system, one for byte transfers and one for word transfers, so there are at least two possible control registers for each register defined. the byte transfer channels are channels 0 ? 3, and their registers are mapped to the byte dma control registers. the word transfer channels are channels 4 ? 7, and their registers are mapped to the word dma control registers. channel 4 is used to connect the two dma devices together in an isa system, so it is not available as a separate channel. command register the functionality of this register is identical to the legacy dma controller, so data is passed through unchanged. mode register data bits 1 ? 0 are reserved. they are written undefined by the master dma. the legacy dma controller expects the channel number encoded in these bits. each target dma channel encodes the lower two bits of its channel number into the lower two bits of the data, replacing the two undefined bits. the functionality of the remainder of this register is identical to the legacy dma controller, so data is passed through unchanged. request register data bits 1 ? 0 are reserved. they are written undefined by the master dma. the legacy dma controller expects the channel number encoded in these bits. each target dma channel encodes the lower two bits of its channel number into the lower two bits of the data, replacing the two undefined bits. the functionality of the remainder of this register is identical to the legacy dma controller, so data is passed through unchanged. b + dh w master clear 000dh 00dah n/a b + eh n/a reserved (note 1) b + fh w single-channel mask 000ah 00d4h 00h b + fh r single-channel mask config cfh config efh 00h note: 1. reads return all zeroes. writes have no effect. table 14. programming model for single target dma channel (continued) target address read/ write register name byte dma address word dma address por value
chapter 5 functional operations 103 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information single-channel mask register in writes to this register, the master dma writes the new mask value in data bit 0. data bits 1, 2, and 3 are reserved and are undefined by the master dma. the legacy dma controller expects the channel number encoded in bits 1 ? 0 and the mask bit passed in bit 2. each target dma channel encodes the lower two bits of its channel number into the lower two bits of the data, replacing bits 1 ? 0. the mask bit written in bit 0 is copied intact to bit 2 and bit 3 is cleared. the functionality of the remainder of this register is identical to the legacy dma controller, so data is passed through unchanged. in reads of this register, the master dma reads the current mask value in bit 0. the legacy dma controller ? s single-channel mask register is write-only, therefore the multi-channel mask shadow register is read. it returns the mask bits for all four channels in the dma controller in such a way that the channel 0 mask is returned in bit 0, the channel 1 mask in bit 1, the channel 2 mask in bit 2, and the channel 3 mask in bit 3. the bit corresponding to the target channel number is copied to bit 0 and the remaining bits are cleared. status register the master dma reads the current terminal count (tc) status value replicated four times in data bits 0 ? 3 and the current channel request (drq) status value replicated four times in data bits 4 ? 7. the legacy dma controller ? s status register returns the terminal count status and request bits for all four channels in the dma controller. the tc bit corresponding to the target channel number is copied to bits 0 ? 3, and the drq bit corresponding to the target channel number is copied to bits 4 ? 7. 5.11.3 dma software commands master clear the functionality of this register is identical to the legacy dma controller, so data is passed through unchanged. 5.11.4 dma addressing each legacy dma channel has two legacy addresses defined to store the base memory address and count information. located at these byte legacy addresses are 16-bit registers. the state of the first/last flip-flop determines which byte (high or low) is being accessed. the target dma does not suffer this problem
104 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information because it has fully decoded these registers. table 15 on page 104 shows the relationship between legacy dma addressing for base, count, and memory page registers. it also shows where this information is programmed into the target dma. for the byte legacy dma, bits 0 ? 7 represent address 0 ? 7. however, for the word legacy dma, bits 0 ? 7 represent address 1 ? 8. this carries forward to the next address byte. the memory page register re-aligns the bit position to the address. this relationship is maintained in the target dma. a target dma can be programmed to be in 8-bit/16-bit transfer mode from its pci configuration space. this mode information defines how the target dma treats the data in the registers. table 15 also defines optional non-legacy addressing extensions for the target. table 15. dma registers legacy channel base address base address memory page count address count address channel 0 0000h 0000h 0087h 0001h 0001h channel 1 0002h 0002h 0083h 0003h 0003h channel 2 0004h 0004h 0081h 0005h 0005h channel 3 0006h 0006h 0082h 0007h 0007h address 1 ? 8 address 9 ? 16 address 17 ? 23 address 1 ? 8 address 9 ? 16 channel 4 00c0h 00c0h n/a 00c2h 00c2h channel 5 00c4h 00c4h 008bh 00c6h 00c6h channel 6 00c8h 00c8h 0089h 00cah 00cah channel 7 00cch 00cch 008ah 00ceh 00ceh above channels map to target address base + 0h base + 1h base + 2h base + 4h base + 5h 8-bit mode address 0 ? 7 address 8 ? 15 address 16 ? 23 address 0 ? 7 address 8 ? 15 16-bit mode address 1 ? 8 address 8 ? 16 address 17 ? 23 address 1 ? 8 address 8 ? 16 non-legacy target dma addressing extensions base address base + 3h count address base + 6h 8-bit mode address 24 ? 31 address 16 ? 23 16-bit mode address 24 ? 31 address 17 ? 23 notes: 1. any target dma that does not support the non-legacy extensions must always return a value of 00h from these locations when read. 2. it is the responsibility of the master dma to support the reserved memory page registers. because the AMD-756 controller impl e- ments subtractive decoding for these registers, master dma blocks that implement them behave as expected by the distributed dma specification.
chapter 5 functional operations 105 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.11.5 pci target dma configuration registers there must be one target configuration register for each target channel in a device, with bit 0 being the channel enable bit. the target base address, along with a matching base address in the master dma indicates the dma channel to which the target dma is mapped. no two target dma channels can be programmed with the same target base address, because bits 6 ? 4 of the base address are read-only values that equal the channel number. the target dma is only required to support at least one transfer size. the first four target dma channels only support 8-bit transfers, so bits 2 and 1 always read 00b. the second four target dma channels only support 16-bit transfers, so bits 2 and 1 always read 01b. no other transfer sizes are supported. non-legacy extended addressing is not supported. the dma target channel accepts writes to bits 31 ? 24 of the address register and bits 23 ? 16 of the count register, with reads from those bits returning zeroes for data. 5.12 isa bus refresh cycle types the AMD-756 controller supports decoupled refresh mode only. the pc/at-compatible refresh period of 15.625 microseconds is supported by dividing the osc signal. the AMD-756 supports only off-board refresh timing. data in dram on the isa bus is refreshed every 15.64 microseconds. a refresh request can be generated by either the AMD-756 controller in pci bus master mode, or by an add-on card in isa master mode. the only difference between the refresh requests is that the requester drives the refresh# pin. the refresh address is put on sa[8:0] by the AMD-756 (regardless of which master currently owns the bus) in response to a low refresh# signal. the sa[16:9] addresses are tri-stated. sa[19:17] are driven low. memr# is asserted by the AMD-756 controller one bclk cycle after refresh# goes asserted. memr# remains low for two bclk cycles. the refresh# signal is negated one bclk period after memr# negates.
10 6 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5.13 fast ide/eide interface the AMD-756 controller includes an ide controller that connects to the primary and secondary port pins as shown in figure 24. the ide controller is accessed through function 1 pci configuration registers. figure 24. ide controller connections 5.13.1 ide drive registers the ide registers are 1f0h through 1f7h for the primary channel and 170h through 177h and 376h for the secondary channel. these registers are not resident in the AMD-756, but are incorporated into the actual drive mechanism. the contents of the ide registers are relatively straightforward, but the legacy ata registers are detailed here for completeness. the address map for these registers is shown in table 16. 5.13.2 ide configuration registers each ide channel has a complete and independent set of configuration registers. the registers for the primary channel and the secondary channel are identical except for their addresses in pci configuration space function 1. the primary channel registers are located at offset 10h ? 1bh. the secondary channel registers are located at offset 18h ? 1fh. ide controller primary port secondary port pci bus
chapter 5 functional operations 107 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.13.3 ultra dma support ultra dma is a data transfer protocol for ata/atapi-4 to be used with read dma and write dma commands and data transfers for packet commands. the AMD-756 controller supports ultra dma/33 transfer mode 0, 1, 2. it also supports mode 3 and 4 defined in a new proposal for ultra dma-66, which doubles the transfer rates to 66 mbytes/seconds. the udma-66 protocol enhances data integrity by use of an 80-pin conductor cable and by crc checking. table 17 lists the cycle times and throughput for the different modes in the udma protocol. table 16. ide register map channel 0 channel 1 type description 1f0h 170h read/write data register (16-bit) 1f1h 171h read-only write-only error register (8-bit) features register (8-bit) (former write compensation register) 1f2h 172h read/write sector count register (8-bit) 1f3h 173h read/write sector number register 1f4h 174h read/write low cylinder number register (8-bit) 1f5h 175h read/write high cylinder number register (8-bit) 1f6h 176h read/write drive/head register (8-bit) 1f7h 177h read-only write-only status register (8-bit) command register (8-bit) 3f6h 376h read-only write-only alternate status register (8-bit) ? contains the same information as the status register at offset 1f7h but does not clear the interrupt or imply interrupt acknowledge device control register (8-bit) ? bit 2 is the software reset bit. bit 1 is the enable bit for the drive interrupt to the host. table 17. ultra dma protocol modes mode cycle time source ultra dma 0 235 ns 16mbytes/second udma-33 1 160 ns 24mbytes/second 2 120 ns 33mbytes/second 3 90 ns 44mbytes/second udma-66 4 60 ns 66mbytes/second
10 8 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information the ultra dma protocol uses the existing signal pins in the ide connector. a number of standard ide signals are redefined when the device is in the udma mode. table 18 lists the ide drive cable interface that are redefined as the ultra dma interface signals. the dior# signal is redefined as dmardy# during a read transaction for transferring data from the udma device to the AMD-756 controller. the AMD-756 uses the dmardy# to signal when it is ready to transfer data and to add wait states to the current transaction. the dior# signal is redefined as strobe during a write transaction when transferring data from the AMD-756 controller to the udma device. this signal is driven by the AMD-756 and data is transferred during each rising and falling edge transition. diow# signal is redefined as stop during read and write transaction. this signal is always driven by the AMD-756 controller and is used to request that a transfer be stopped. iordy s ignal is redefined as strobe during a read transaction for transfer. this signal is driven by the udma device and data is transferred during each rising and falling edge transition. dior# signal is redefined as dmardy# during a write transaction when transferring data from the AMD-756 to the udma device. the udma device uses dmardy# to signal when it is ready to transfer data and to add wait states to the current transaction. a read dma or write dma command or data transfer for a packet command is accomplished through a series of input or output data bursts. each burst has three phases of operation, the burst initial phase, the data transfer phase, and the burst termination phase. table 18. ultra dma interface signal redefinition standard ide signal driven by udma/33/66 read definition udma/33/66 write definition AMD-756 ? signal dior# host dmardy# strobe diow# host stop# stop# iordy device strobe dmardy#
chapter 5 functional operations 109 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the burst initial phase begin with the assertion of dmarq by the device and ends when the sender toggles strobe to transfer the first data word. the data transfer phase is then in effect until the burst termination phase, which begins either when the host asserts stop or the device negates dmarq. the device asserts ddrq to initiate a burst. the host asserts ddack# when it is ready to begin the requested burst. for read cycles, the host releases data, the device asserts dstrobe, and the host negates stop and asserts dmardy#. the device then drives the first word of the data transfer onto data. the data is transferred when the device negates dstrobe. for write cycles, the device asserts ddmardy# after the host has negated stop. the host drives the first word of the data transfer onto data. the data is transferred when the host toggles hstrobe. the device (reads) or host (writes) continues to drive a data word onto data and toggles dstrobe to latch the data until the data transfer is complete or the burst is paused. either the device or the host can pause a burst transfer. the device pauses the read dma burst by halting dstrobe toggling, and resumes the burst by toggling dstrobe again. the host pauses a read burst by negating hdmardy# and resumes the burst by reasserting hdmardy#. either the device or the host can terminate a burst. a burst must be paused before it can be terminated. the host responds by asserting stop and with the device negating dmardy#. the device can then stop the burst by negating ddrq and host acknowledges by asserting stop. the transmitter then drives the strobe signal to a high level. the host then places the result of its crc (cyclic redundancy check) on data and negates ddack#. the data is latched in the device at the negating edge of ddack#. udma33/66 protocol changes due to the shorter cycle times of the udma-66 protocol, more data words can be sent after the dmardy signal is set to low. with udma-33, modes 2, 1, and 0 could receive at least two data words whenever the receiver entered or resumed an ultra dma burst. with udma-66, modes 3 and 4 can receive at least three data words whenever the receiver enters or resumes an ultra dma burst.
110 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information the udma-66 proposal specifies a new 80-pin conductor cable, which is required for modes 3 and 4. this conductor cable reduces crosstalk by adding 40 additional grounds between the 40 standard ata signal and ground lines. to avoid running at 66 mbytes/second without the proper cable, the host must verify the cable type for modes 3 and 4. the 80-pin cable can be detected either by using the state of the pdiag#:cblid# signal or through the identify device command or identify packet device command. to detect the state of the of the pdiag#:cblid# signal, the host checks to see if pdiag#:cblid# is grounded or pulled up. if this signal is grounded, an 80-pin conductor cable is installed, because this signal is grounded in the 80-pin conductor cable host connector. if this signal is pulled up, a 40-pin conductor cable is installed, because this signal is connected to the udma-66 devices and is pulled up through a 10-kohm resistor at each device. to detect the 80-pin cable with the identify device command or identify packet device command, a capacitor is installed from pdiag#:cblid# to ground. the udma-66 drive detects the presence or absence of this capacitor after receiving the identify device command or identify packet device command. the udma-66 drive then discharges the capacitor and measures the signal line. if an 80-pin conductor cable is installed, the udma-66 drive detects this signal as pulled up, because this signal is not connected to the udma-66 drive in the 80-pin cable. if a 40-pin cable is installed, the rise time of the signal is slow enough that it can be sampled by the udma-66 drive while it is below v il . the capacitor test results are reported to the host in the data returned by the identify device command or identify packet device command.
chapter 5 functional operations 111 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.14 power management support 5.14.1 power management subsystem the power management function of the AMD-756 controller is indicated in the following block diagram. this block includes logic for most of the multiplexed-function pins-such as general- purpose i/o (gpio) pins, the power management (pm) pins, system management bus (smbus) pins, and the plug and play (pnp) pins-as well as the logic for acpi-compliant power management for desktop systems. register access to most of this logic is contained in the configuration space for function 3 and the 256-byte i/o space (defined by the configuration space) called i/o mapped power management +xx. here is a general diagram of this block. figure 25. power management and general purpose i/o stpclk# gp inputs power management and general purpose i/o block hardware traps system power state controller (spsc) timers registers smbus logic throttling logic system inactivity timer smi# to apic block gp outputs sci# to pic/apic pwrbtn# pwron# pme#
112 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 26. basic power management block diagram 5.14.2 power plane management the following table summarizes the events that can be detected by the system management logic and the registers in which hardware responses can be enabled for each. the columns are sts, where the status bits are accessible, evt, where the grouped statuses can be read, sci/smi en, where the acpi interrupts can be enabled, smi_en, where the smi interrupts can be enabled, sit_en, where the events can be enabled to reload the system inactivity timer, and the resume columns which show where the registers to enable the resume events from c2, c3, pos, and soff to fon (see the system power state controller section, below). 20 re-trigger timers status, enables 20 hardware traps pwron#, cpustop#, pcistop#, cache_zz#, dcstop#, suspend#, cpusleep# smi# and sci# input pins interrupts pci bus masters system inactivity timer status, enables stpclk# registers, throttling logic stpclk# system power state controller status, enables
chapter 5 functional operations 113 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 19. smm events events sts event evt sci/smi en smi only smi_en reload sit_en resume pos en resume c2-c3 en resume soff en smbus host com- plete/error pme0 i/o mappe d power man- age- ment +28h i/o mapped power manage- ment +e2h i/o mapped power manage- ment +2ah smbus host as tar- get transfer i/o mapped power manage- ment +e0h i/o mapped power manage- ment +e2h i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h smbus snoop match i/o mapped power manage- ment +e0h i/o mapped power manage- ment +e2h i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h smbalert# pin i/o mapped power manage- ment +e0h i/o mapped power manage- ment +e2h i/o mapped power manage- ment +16h irq[15:0] i/o mapped power manage- ment +b4h intr (unmasked irqs) i/o mapped power manage- ment +b4h bit[2] i/o mapped power manage- ment +16h pci bus masters i/o mapped power manage- ment i/o mapped power manage- ment +b4h i/o mapped power manage- ment +04h bit[1] (c3)
114 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 20 hardware traps i/o mapped power manage- ment +a8h i/o mappe d power man- age- ment +28h i/o mapped power manage- ment +ach i/o mapped power manage- ment +2ah i/o mapped power manage- ment +b0h 20 re-trigger timers time out i/o mapped power manage- ment +a0h i/o mappe d power man- age- ment +28h i/o mapped power manage- ment +a4h i/o mapped power manage- ment +2ah system inactivity timer time out i/o mapped power manage- ment +28h i/o mapped power manage- ment +22h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h usb bus resume event i/o mapped power manage- ment +24h i/o mappe d power man- age- ment +28h i/o mapped power manage- ment +25h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h 4 usb transaction types i/o mapped power manage- ment +24h i/o mapped power manage- ment +25h acpi timer overflow i/o mapped power manage- ment i/o mapped power manage- ment +02h table 19. smm events (continued) events sts event evt sci/smi en smi only smi_en reload sit_en resume pos en resume c2-c3 en resume soff en
chapter 5 functional operations 115 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power button over- ride i/o mapped power manage- ment i/o mapped power manage- ment +26h (off) bios-os lock i/o mapped power manage- ment, bit[28] i/o mapped power manage- ment +02h i/o mapped power manage- ment +2ah software smi i/o mapped power manage- ment +28h i/o mapped power manage- ment +2ah 18 gpio inputs i/o mapped power manage- ment +d4h i/o mappe d power man- age- ment +28h i/o mapped power manage- ment +d8h i/o mapped power manage- ment +2ah real-time clock irq i/o mapped power manage- ment i/o mapped power manage- ment +02h i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h pwrbtn# pin i/o mapped power manage- ment i/o mapped power manage- ment +02h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h extsmi# pin i/o mapped power manage- ment +28h i/o mapped power manage- ment +22h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h table 19. smm events (continued) events sts event evt sci/smi en smi only smi_en reload sit_en resume pos en resume c2-c3 en resume soff en
116 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information pme# pin i/o mapped power manage- ment +28h i/o mapped power manage- ment +22h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h ri# pin i/o mapped power manage- ment +28h i/o mapped power manage- ment +22h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h slpbtn# pin i/o mapped power manage- ment i/o mapped power manage- ment +02h i/o mapped power manage- ment +2ah i/o mapped power manage- ment +16h i/o mapped power manage- ment +26h therm# pin i/o mapped power manage- ment +28h i/o mapped power manage- ment +22h i/o mapped power manage- ment +2ah table 19. smm events (continued) events sts event evt sci/smi en smi only smi_en reload sit_en resume pos en resume c2-c3 en resume soff en
chapter 5 functional operations 117 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.14.3 sci and smi control there are three categories of events that generate sci/smi interrupts. they are time-outs of device monitors-when a peripheral has not been accessed for a period of time-hardware traps, and input pins. figure 27 shows how the control for the sci/smi interrupts is configured. figure 27. sci/smi control the AMD-756 controller usb block also provides a source of smi that is ored into the logic. the serial irq logic can generate smis as well. smi# and sci# go to the pci/apic blocks to generate cpu interrupts. 5.14.4 system inactivity timer any of the hardware traps, irq lines, or pci bus master activity can reload the system inactivity timer. if the timer is enabled and decrements to zero, an interrupt is generated. 5.14.5 throttling logic throttling refers to the act of asserting stpclk# to the cpu for a specified percentage of time in order to reduce the power being consumed by the cpu. once throttling is started, stpclk# looks like a clock with a period of 244 microseconds (based on 8 cycles of the 32.768 khz. clock) and a duty cycle as set status bits 20 re-trigger timers set status bits 20 hardware traps serial irq smi, usb_smi smi# sci# 1 0 sci_en sci path smi path set status bits input pins or or enable enables smi# enables enables smi# enables enables smi# enables or enable
118 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information specified by control registers function 3 offset 50h and i/o mapped power management + 10h. two types of throttling are possible: normal and thermal. normal throttling is controlled by software. thermal throttling is controlled by the therm# pin. if both are enabled to occur at the same time, then the duty cycle specified for thermal throttling is used. throttling is ignored in the soff, c2, c3, and pos power states. if throttling is enabled when entering these states, it stops, once the state is entered. after exiting the state, throttling continues. 5.14.6 system power state controller (spsc) the system power state controller (spsc) supports the states shown in table 20. figure 28 shows the power state transitions. mechanical off: moff. moff is the state when vdd_soft is not powered. this can happen at any time, from any state, due to the loss of power to the vdd_soft plane (e.g., a power outage, the power supply is unplugged, or the power supply ? s mechanical switch). when power is applied to this plane, then the system transitions to either soff or fon, depending on whether the pwron# pin has a pull-up or a pull-down resistor on it. the only resume event that is enabled after the transition from moff to soff is from pwrbtn#. table 20. power states state vdd3 vdd_soft vdd_rtc notes full on (fon) on on on low-power state initiated by cpu. c2 on on on all resume events available. c3 on on on all resume events available. power on suspend (pos) on on on all resume events available. soft off (soff) off on on usb transaction and irq resume events not available (however usb resume event available). mechanical off (moff) off off on no resume events available.
chapter 5 functional operations 119 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 28. power state transitions soft off: soff. the soft off state appears to be ? off ? to the user. AMD-756 controller's vdd_soft plane is powered, but vdd3 is not. the system normally uses pwrbtn# to transition from soff to fon. but AMD-756 also allows smbus activity, usb resume events, the real-time clock alarm, the extsmi# pin, the slpbtn# pin, and the pme# pin to be enabled to cause this transition. all of the soff-to-fon enables are found in i/o mapped power management +26h. snoop-capable clock control: c2 . in c2, the cpu's internal clock is disabled via stpclk#. the state is controlled by i/o mapped power management +50h bits[7:0]. per the acpi specification, the cpu's cache can be snooped while in this state (however, if the cache_zz function is enabled, the l2 cache can not be snooped when in c2). the hardware exits this state when any of the enabled resume events specified by i/o mapped power management+16h occur. these include smbus activity, various pin transitions, intr interrupts, smi interrupts, system inactivity timer time out, and the usb- defined resume event. snoop-disabled clock control: c3. in c3, stpclk# is asserted along with a few other clock control pins that result in a state power failure moff mechanical off soff soft off pwron# set high c2 stop-grant condition (cache_zz may be used) c3 c2 plus clock control (cpustop#, pcistop#, dcstop#, cpusleep#) pos clock-control based power reduction and sleep state (suspend#) cpu initiated (pm14) resume event cpu initiated (pm15) cpu initiated (pm04) resume event resume event resume event cpu initiated (pm04) or pwr override button fon full on
120 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information that prevents the processor ? s cache ? s from being snooped. the state is controlled by i/o mapped power management +50h bits[15:8]. these include cpustop#, which halts the cpu ? s clock via the system pll chip, pcistop#, which halts the system ? s pci clocks (except the one to the south bridge), dcstop#, which causes the dram controller to prepare for its host clock to stop by initiating self refresh cycles to system memory, and cpusleep# which places the cpu into deep sleep. the resume events for c3 are the same as c2 except that pci bus master requests are added. power on suspend: pos. the pos state is treated similarly to c3 by the AMD-756 controller. the state is controlled by i/o mapped power management +50h bits[23:16]. the suspend# pin is typically in this state, asserted along with all the enabled clock controls, which can be used control an external power plane. the pos resume events are the same as for c2 and c3, specified by i/o mapped power management +16h. moff to fon and soff to fon figure 29. mechanical off to full on vdd_soft power pwrgd pcirst# rstdrv t4 t1 cpurst moff to fon t3 rst_soft pwron# t2
chapter 5 functional operations 121 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 30. soft off to full on moff to soff the timing diagram for this sequence is similar to the first part of the moff to fon sequence. however, pwron# rises with vdd_soft and is held high for the entire duration; thus, the other reset signals, pwrgd, pcirst#, rstdrv, and cpurst, never transition. c2, c3, or pos to soff this transition can be initiated by software via i/o mapped power management +04h or by the power-button override event. these both cause pwron# to go high. the assumption is that the power supply will respond by de-asserting pwrgd and dropping power to the system ? s main power supplies, vdd3 power pwrgd pcirst# rstdrv t4 t5 cpurst soff to fon t3 pwron# resume event t2 table 21. power transition times for figures above t minimum maximum t1 25ms 50 ms t2 50 ms t3 1.8 ms t4 1.5 ms t5 32 s 64 s
122 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information including vdd3. vdd_soft must remain valid throughout this transition. immediately after pwrgd goes low, pcirst#, rstdrv, and cpurst become asserted. as vdd3 drops, these reset signals become invalid transitions between fon and c2, c3, or pos function 3 offset 50h specifies the definition of these transitions as enables for the following eight signals: cpurst, suspend#, cpusleep#, pcistop#, cpustop#, dcstop#, cache_zz. any of these signals can be enabled for the transition to any of the three low-power states. the transition to c2, c3, and pos occurs as follows, for each of the enabled pin controls: n cpu initiation. first, software commands that the proper state transition take place as follows: the transition to c2 is initiated by reading i/o mapped power management + 14h, the transition to c3 is initiated by reading i/o mapped power management + 15h, and the transition to pos is initiated by setting i/o mapped power management + 04h bit [slp_typ] to ? b010 and writing i/o mapped power management + 04h bit [slp_en] high. n stop grant. the AMD-756 controller then asserts stpclk# and waits for the stop-grant cycle from the pci bus (a special cycle as specified by function 3 offset 41h bit [stpgnt]) to be completed. n cache_zz. four pclk cycles after stop-grant, cache_zz is asserted. n dcstop# . eight pclk cycles after stop-grant, dcstop# is asserted. n cpusleep#. 64 pclk cycles after stop-grant, cpusleep# is asserted. n cpustop# and pcistop#. 68 pclk cycles after stop- grant, cpustop# and pcistop# are asserted. n suspend#. 80 pclk cycles after stop-grant, suspend# is asserted. resume events are enabled by i/o mapped power management + 16h and, in the case of c3, i/o mapped power management +03h bit[1]. here is the resume sequence, once an enabled resume event occurs, if the suspend# pin is utilized: n suspend#. immediately after the resume event, the suspend# pin is de-asserted along with cpusleep# and
chapter 5 functional operations 123 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information stpclk#. if cpurst is enabled to be asserted by function 3 offset 50h, it is asserted at this time as well. n cpustop# and pcistop#. 17.7 milliseconds after suspend#, cpustop# and pcistop# are de-asserted. n dcstop#. about one millisecond after cpustop# and pcistop are de-asserted, dcstop# is de-asserted. n cpurst. 4 pclk cycles after dcstop#, cache_zz and cpurst are de-asserted. here is the resume sequence, once an enabled resume event occurs, if the suspend# pin is not utilized, but dcstop#, pcistop# or cpustop# is utilized: n cpustop# and pcistop#. cpustop# and pcistop# are de-asserted immediately after the resume event. n dcstop#. about one millisecond after the resume event, dcstop#, cpusleep#, and cache_zz are de-asserted. n stpclk#. 4 pclk cycles after dcstop#, stpclk# is de- asserted. here is the resume sequence, once an enabled resume event occurs, if the suspend#, pcistop#, cpustop#, and dcstop# pins are not utilized: n cache_zz. 4 pclk cycles after the resume event, cache_zz is de-asserted. n stpclk#. 4 pclk cycles after cache_zz, stpclk# is de- asserted. 5.14.7 serial irq protocol the AMD-756 controller supports the serial irq protocol. this logic controls the serirq pin and outputs irqs to the pic/apic blocks. this logic runs off of pclk. it is specified by function 3 offset 4ah. the serial irq logic does not provide support for generating irq0, irq2, irq8, or irq13. 5.14.8 smbus the AMD-756 controller includes a complete system management bus, or smbus, interface. smbus is a two-wire serial interface used to communicate with system devices such
124 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information as temperature sensors, clock chips, and batteries. the registers that specify this bus are i/o mapped power management +e0h through i/o mapped power management +efh. the smbus interface includes a host controller and a host-as- target controller. host bus controller the host can generate cycles over the smbus as a master. software accomplishes this by setting up i/o mapped power management +e2h bit[cyctype] to specify the type of smbus cycle desired and then (or concurrently) writing a 1 to i/o mapped power management +e2h bit[hostst]. then a cycle is generated with the various address, command, and data fields as specified by the registers called out in i/o mapped power management +e2h bit[cyctype]. writes to the host controller registers i/o mapped power management +e2h bits[3:0], i/o mapped power management +e4h, i/o mapped power management +e8h, and i/o mapped power management +e9h are illegal while the host is busy with a cycle. if a write occurs to i/o mapped power management +e2h while i/o mapped power management +e0h bit[hst_bsy] is asserted, then the four lsbs be ignored. writes to i/o mapped power management +e4h, i/o mapped power management +e8h, and i/o mapped power management+e9h while i/o mapped power management +e0h bit[hst_bsy] is asserted are ignored (the pci cycle is completed, but no data is transferred). if an smbus-defined time out occurs while the host is master of the smbus, then the host logic attempts to generate a smbus stop event to clear the cycle. also, i/o mapped power management +e0h bit [to_sts] is set to indicate what happened. host-as-target controller the host-as-target controller responds to word-write accesses to either the host address specified by i/o mapped power management +eeh or the snoop address specified by i/o mapped power management +efh. in either case, if the address matches, then the subsequent data is placed in i/o mapped power management +ech and i/o mapped power management +eah. in the case of snoop accesses, the command information is stored in i/o mapped power management +ech bits[7:0] and the data is stored in i/o mapped power management +eah bits[15:0]. in the case of
chapter 5 functional operations 125 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information addresses that match the i/o mapped power management +eeh host-as-target address register, then the smbus master ? s address is stored in i/o mapped power management +ech bits[7:1]-if the master has a 7-bit address-or i/o mapped power management +ech bits[15:1]-if the master has a 10-bit address. after the address match is detected, the target logic waits for the subsequent stop command before setting the appropriate status bit in i/o mapped power management +e0h bits[hslv_sts, snp_sts]; however, if a time out occurs during the cycle, after the address match is detected, then the appropriate bit in i/o mapped power management +e0h bits [hslv_sts, snp_sts] will not be set. if one of the target status bits, i/o mapped power management +e0h bits[hslv_sts, snp_sts], are set and another access to the host target controller is initiated, then it is not acknowledged (via the first smbus acknowledge cycle) until the status bit is cleared. the host-as-target controller operates in the c2, c3, pos, and soff modes; it can be used to generate interrupts that wake the system and place it into fon. smbalert. the host controller supports the smbalert# signal. if this signal is asserted, then, according to the smbus specification, software must determine the source by sending a host read cycle to the alert response address, ? b0001_100. if the smbus host controller detects this address for a read cycle with i/o mapped power management +e2h bit[cyctype] set to receive byte ( ? b001), then it stores the address returned by the smbalert# target in i/o mapped power management +e6h bits[7:0]. if bits[7:1] of this address are ? b1111_0xx, indicating a 10-bit address, then it stores the next byte from the target in i/o mapped power management +e6h bits [15:8]. 5.14.9 plug and play the AMD-756 controller supports three pnp irqs, two pnp chip selects, and one pnp dma select. the registers that specify these are function 3 offsets 44h and 46h. the pnp pins are multiplexed with other functions; the control registers that specify the functions (the gpio control registers i/o mapped power management +c0h through i/o mapped power
126 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information management +d1h) must be set up appropriately for the pnp functions to operate. 5.14.10 general-purpose i/o the general-purpose i/o pins, gpio[17:0], can be assigned to be inputs, outputs, interrupt generators, or bus controls. these pins can be programmed to be general-purpose i/o or to be a pre-determined alternate function (see the pin summary section of this document). these pins are all named after one of their alternate functions. there is one register for each pin, i/o mapped power management +[c0h:d1h], that controls the state of each. irq status and enables are available for each pin in registers i/o mapped power management +d4h and i/o mapped power management +d8h. 5.14.11 general-purpose i/o functions as a general-purpose i/o pin, these pins have the following options: n outputs. ? can be set high or low. can be controlled by gpio output clocks 0 or 1 (see i/o mapped power management +dch). n inputs. active high or active low programmable. sci or smi irq capable. can be latched or not latched. inputs can be debounce protected. here is the basic format for all the general-purpose i/o pins. the input path is not disabled when the output path is enabled or the pin is used for an alternate function. however, when a gpio function is selected, the alternate function signal is forced to the negated state.
chapter 5 functional operations 127 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 31. general-purpose i/o logic debounce the debounce circuit consists of a three bit counter clocked off of c256hz, a 4-millisecond cycle-time clock. the input signal to the circuit is the output of the active-high-active-low multiplexer. the counter is asynchronously cleared by the low state of the input signal and allowed to count when the input signal is high. if the counter increments from ? h0 to ? h4, then the counter stops and the output goes high. thus, the input signal must be high for 12 to 16 milliseconds before the output signal is asserted. gpio output clocks there are two gpio output clocks, numbered 0 and 1. they are specified by i/o mapped power management +dch. each output clock includes a 7-bit programmable high time, a 7-bit programmable low time, and the counter can be clocked by one of four frequencies. see table 22. the output of the two gpio output clocks can be selected to drive the output of any of the gpio pins. they can be used to blink leds or for other functions. latch ltch_sts rtin activehi vcc output flip-flop debounce circuit latch q d le gpio output clocks 0 and 1 output mode to interrupt generator or alternative logic (i/o apic, slpbtn#, extsmi#, ri#, pnpirq ? s, therm#) output path input path 1 0 1 0 1 0 debounce
128 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information square wave generator. the intirq8# pin, controlled by i/o mapped power management +d0h, includes one additional potential functions, sqwave. this is a square wave output, the frequency for which is specified by function 3 offset 4eh. the square wave generator uses a counter that is clocked by the 32 khz. clock. 5.14.12 am d-751 ? controller power management the amd-751 system controller flushes all activity before allowing the stop-grant cycle onto the pci bus to the AMD-756. after that, the AMD-756 controller can force the amd-751 device into a clock-stopped mode with dcstop#. the amd-751 includes self refresh mode so that the host clock can be allowed to stop. the amd-751 includes the pci arbiter disable registers described in the acpi specification in order to support the c3 low-power state. 5.14.13 vdd_soft registers and logic the following is a list of the register bits and logic on the vdd_soft power plane: registers function 3 offset 48h bits[intrtc, pwron]; i/o mapped power management bits [pbor_sts, rtc_sts, slpbtn_sts, pwrbtn_sts]; i/o mapped power management +1ch bits[7:0]; i/o mapped power management +24h bits[usb_rsm_sts]; i/o mapped power management +26h table 22. gpio output clock options i/o mapped power management +dch clk[1,0]base base clock period output high time range output low time range ? b00 250 microseconds 250 s to 32 ms 250 s to 32 ms ? b01 2 milliseconds 2 ms to 256 ms 2 ms to 256 ms ? b10 16 milliseconds 16 ms to 2 sec 16 ms to 2 sec ? b11 128 milliseconds 128 ms to 16.4 sec 128 ms to 16.4 sec
chapter 5 functional operations 129 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information (all); i/o mapped power management +28h bits [ri_sts, extsmi_sts, pme_sts]; i/o mapped power management + c0h; i/o mapped power management + c1h; i/o mapped power management + c3h; i/o mapped power management + cch; and i/o mapped power management + ceh. logic gpio output blink clocks; the logic associated with pins pwrbtn#, pwron#, pme#, ri#, smbus[c,d], extsmi#, slpbtn#, and pwrgd (including gpio logic); the state machine to transition between the soff and fon states; smbus target logic; and the usb resume-event detect logic. this logic is functional and the registers are preserved when in any power state, including soff, except moff. 5.14.14 rtc and cmos memory the real-time clock includes a 32 khz. oscillator, a clock and calendar timer, an alarm (which generates an interrupt when a specified time occurs), and 256 bytes of non-volatile ram. it is register compatible with the real-time clock found in the original at design (which used the mc146818). also, it is updated to meet acpi ? s real-time clock requirements. power the real-time clock includes its own power plane, vdd_rtc, which is expected to be powered by an external 3.3-volt lithium battery. when the vdd_soft plane is powered, the system is required to power the real-time clock circuitry with that plane such that the vdd_rtc leakage current is less than 0.5 microamps. it is a requirement that cpu accesses to the real- time clock logic be disabled when the vdd_soft plane is not powered. it is also a requirement that the vdd_soft plane be capable of being arbitrarily powered up and down without the possibility of disturbing the rtc logic or causing erroneous writes to the real-time clock register set. the vdd_rtc power plane is required to not be damaged when it is not powered while the other cobra power planes are powered. conversely, vdd_rtc is allowed to be powered while any other planes are not powered. when operating on the battery ? s supply, the rtc section is required to consume no more than 0.5 microamps of current
130 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information (this gives 11.4 years of life with a typical 50 milliamp-hour battery). oscillator the real-time clock includes a 32.768 khz. oscillator that is used to keep time. the oscillator circuit is designed to be accurate to within 10 parts per million over the external temperature and capacitance ranges. this provides for a time loss of less than 30 seconds per month. switching the real-time clock power source between vdd_rtc and vdd_soft does not affect the operation or frequency of the oscillator. this oscillator is required to be present regardless of whether the internal or an external real-time clock is used. vdd_soft reset the rtc logic generates a reset signal to vdd_soft power plane when that plane is detected to power up. it is called rst_soft. rst_soft is required to last between 25 and 50 milliseconds after vdd_soft is detected to be greater than 2.5 volts. this reset is required to occur when the vdd_rtc plane is powered as well; the rtc battery may be dead or the external rtc may be being used so the rtc power plane would always power up with the vdd_soft plane. self reset there is no external reset signal for the logic powered by vdd_rtc. the circuitry generates its own internal reset signal when vdd_rtc power is applied to the ic such that it is guaranteed to power up in a functional state. the application of vdd_rtc power is allowed to be very noisy ? rapidly going up and down ? as a battery is being inserted into a socket. the self reset signal is allowed to be up to two seconds long. the self reset is applied to the reset for the vdd_soft plane, if that plane is powered (i.e., if the battery is missing or dead and vdd_soft is powered, then the logic is capable of resetting both planes properly). external real-time clock this logic is also required to be able to operate properly when an external real-time clock is used. in this situation, no battery is connected to the vdd_rtc plane. instead, the vdd_rtc plane is connected to vdd_soft. after pwrgd reset, the system detects that an external real-time clock is present and selects the pins for this function. see function 3 offset 48h bit[intrtc]. new acpi requirements section 4.7.2.4 of the revision 1.0 acpi specification describes the new requirements for the real-time clock. some of these are
chapter 5 functional operations 131 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information listed as optional. however, the AMD-756 controller implements all of these features. the day alarm, month alarm, and centenary value are stored in cmos ram address space. prdy the rtc ? s counter chain is frozen from counting, if enabled to do so in function 3 offset 4ch bit[rtc_dis], when prdy is asserted. a complete cmos table can be found in chapter 7. 5.15 universal serial bus controller (usbc) introduction the usb controller, usbc, is a complete host controller as defined by the universal serial bus, usb, 1.0 specification and the openhci standard developed by compaq, microsoft, and national semiconductor. openhci specifies the interface between the host controller driver, hcd, and the host controller, hc. usbc contains an integrated root hub with 4 usb ports, pci interface, and a host controller core. keyboard and mouse legacy support are also included for dos compatibility with usb devices. pci interface the openhci host controller is connected to the system by the pci bus. the design requires both master and target bus operations. as a master, the usbc runs cycles on the pci bus to access endpoint descriptors, eds, and transfer descriptors, tds, as well as transferring data between memory and the local data buffer. the usbc is a pci target when it decodes cycles to its internal pci configuration registers or to its internal pci memory mapped i/o registers. the following table identifies the cycle types initiated by the usbc as a master and accepted by the usbc as a target. table 23. rtc cmos addresses cmos ram offset function range for binary mode range for bcd mode 7dh date alarm 0h-1fh 01h-31h 7eh month alarm 01h-0ch 01h-12h 7fh century field 13h-63h 19h-99h
132 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 24. pci commands supported by the usbc note: *only a single doubleword is accepted after which the cycle is retried. pci master for write cycles, the command issued is memory write unless the requested transfer is exactly one cache line and the cache line size is set to 32 bytes, in which case the command is memory write and invalidate. the byte enables are synthesized for the first and last doublewords using the begin address and number of bytes to calculate them. all doublewords between the first and last have all byte enables asserted. for read cycles, the command issued depends on the transfer size and the value of the cache line size within the configuration space. transfers that cross a cache line boundary use the memory read multiple command. transfers that cross a quadword boundary use the memory read line command. all other transfers use the memory read command. the address used in the master cycle is stored in a register at the initial request of the cycle. when the pci cycle commences, the upper 30 bits of the register are sent to the pci bus, with the lower two bits always being 0h. after each successful pci transfer the address register is incremented by the number of bytes transferred. thus, in case of a disconnect, retry, or time- out of the cycle the address is ready for the resumption of the cycle. pci target the usbc target state machine and interface logic support fast back-to-back cycles. the usbc does not require an idle cycle between a write to another target and a usbc target access. device selection the usbc uses medium decode timing when asserting devsel# to claim a pci transaction whose address c/be[3:0]# command type target support master support 0010 i/o read yes no 0011 i/o write yes no 0110 memory read yes yes 0111 memory write yes yes 1010 configuration read yes no 1011 configuration write yes no 1100 memory read multiple yes* yes 1110 memory read line yes* yes 1111 memory write and invalidate yes* yes
chapter 5 functional operations 133 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information corresponds to the base address and offset of an internal address. when the usbc asserts devsel#, it does not negate devsel# until the transaction ends on the bus. the end of the bus transaction is indicated by frame# sampled negated, irdy# sampled asserted, and either trdy# or stop# sampled asserted. write cycles the usbc interprets command codes c/be[3:0]# = 0111 (memory write) and 1111 (memory write and invalidate) as write cycles. the usbc does not perform write gathering for pci write cycles; all writes are posted and strong write ordering is maintained. while a posted write cycle is still in process, subsequent target read or write cycles are either held off with wait states until the posted write completes, or the cycle is ? retried ? if it requires more than 16 waitstates. if a master attempts to burst more than one doubleword to the usbc in a cycle, the usbc disconnects the cycle after the first doubleword is written. the pci specification allows any contiguous or non-contiguous combination of byte enables. as a target, the usbc ignores the byte enables for memory write cycles. all memory-mapped registers within the usbc are defined as doublewords. read cycles the usbc interprets command codes c/be[3:0]# = 0110 (memory read), 1100 (memory read multiple), and 1110 (memory read line) as a read cycle. read cycles are not posted. if the cycle can be accepted, the usbc claims the cycle by asserting devsel#, and then holds the pci bus in wait states by holding trdy# negated until the data is ready. if a master attempts to burst more than one doubleword from the usbc in a cycle, the usbc disconnects the cycle after the first doubleword is read. configuration cycles the usbc interprets command codes c/be[3:0]# = 1010 and 1011 as configuration read and configuration write cycles respectively. the usbc can accept any combination of byte enables for configuration write cycles. locked cycles the usbc does not implement lock cycles.
134 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information abort cycles the usbc pci target state machine performs pci target abort cycles for any i/o cycle in which the byte enables do not correspond to the low two address bits. generation of serr# the usbc asserts serr# internally when it detects a pci address parity error and it is the agent receiving data, if parity is enabled. serr# is also asserted whenever the serr enable bit (bit 8 of the pci command register) is enabled and a target abort is received, a target abort is signaled, or master abort is signaled. this serr# internal signal is used to generate an nmi. generation of stop# the usbc only asserts stop# to retry a transaction when it is the target, never to abort it. 5.15.1 usbc miscellaneous functions power switching a root hub controls power to the downstream ports. the usbc implements global power control, which means that all port ? s power status, portpowerstatus, is controlled by set/clearglobalpower commands. individual port power switching as well as no power switching modes are also implemented, but individual port power switching signals are not brought out of the usbc. the table below shows the power switching configurations in the descriptor registers. the output pin pwren controls global power switching. over-current protection over-current is reported on a global basis. input pin ovrcur is read directly through overcurrentindicator in hcrhstatus . over-current mode is configured in hcrhdescriptora by noovercurrentprotection and overcurrentprotectionmode. when in individual over-current mode, ovrcur status is table 25. power switching mode mode no power switching power switching mode port power control mask no switching 1 - - global switching 0 0 - individual port switching 0 1 1 global switch in individual switching mode 010
chapter 5 functional operations 135 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information reported through the portovercurrentindicator in hcrhportstatus for test purposes. when an over-current condition occurs overcurrentindicatorchange is set and power is disabled. if port power is not switched (nopowerswitch), the port power status is not affected by an over-current condition. legacy keyboard and mouse support to support applications and drivers in non-usb aware environments (e.g. dos) the usbc provides hardware support for the emulation of a ps/2 keyboard and/or mouse by their usb equivalents. when keyboard emulation is enabled, the usbc intercepts i/o accesses to port 60 and port 64. the keyboard controller must use subtractive decode. keyboard/mouse input when a successful transfer of data has occurred from the keyboard, the transfer descriptor is moved to the done queue by the usbc. at the beginning of the next frame when the interrupt associated with the transfer completion is to be signaled, an interrupt is generated. system software should be designed to set the interruptrouting bit in hccontrol to 1, so that the interrupts result in an smi. on receipt of the smi the emulation software removes the transfer descriptor from the done queue, clears the usbc irq, and translates the keyboard/mouse data into an equivalent ps/2-compatible sequence for the application software. for each byte of ps/2 compatible data that is to be presented to the applications software, the emulation code writes to the hceoutput register. the emulation code then sets the appropriate bits in the hcestatus register (normally sets outputfull for keyboard data and outputfull plus auxoutputfull for mouse data.) if keyboard/mouse interrupts are enabled, setting the hcestatus register bits causes generation of an irq1 for keyboard data and irq12 for mouse data. the emulation code then exits and waits for the next emulation interrupt. when the host cpu exits from smm, it can service the pending irq1/irq12. this normally results in a read from i/o port 60h. when i/o port 60h is read, the usbc intercepts the access and returns the current contents of hceoutput . the usbc then also clears the outputfull bit in hcestatus , and de-asserts irq1/irq12. if the emulation software has multiple characters to send to the application software, it sets the characterpending bit in the
136 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information hcecontrol register. this causes the usbc to generate an emulation interrupt on the next frame boundary after the application has read from port 60h ( hceoutput .) keyboard output keyboard output is indicated by application software writing data to either i/o address 60h or 64h. upon a write to either address the usbc will capture the data in the hceinput register and, except in the case of a gate a20 sequence, update the hcestatus register ? s inputfull and cmddata bits. when the inputfull bit is set, an emulation interrupt is generated. upon receipt of the emulation interrupt, the emulation software will read hcecontrol and hcestatus to determine the cause of the emulation interrupt and perform the operation indicated by the data. emulation interrupts emulation interrupts are caused by reads and writes of the emulation registers. interrupts generated by the emulation hardware are steered by the usbc to either an smi or the standard interrupt. steering is determined by the setting of the interruptrouting bit in the hccontrol register. emulation interrupts for data coming from the keyboard/mouse are generated on frame boundaries. at the beginning of each frame, the conditions which define asynchronous emulation interrupt are checked and, if an interrupt condition exists, the emulation interrupt is signaled to the host at the same time as the interrupts coming from normal usb processing. this has the effect of reducing the number of smis that are generated for legacy input to no more than 1,000 per second. although still somewhat large, this number of interrupts is less than the number that could be generated if emulation interrupts were not merged with the normal usbc interrupts. mixed environment interrupts a mixed environment is one in which a usb device and an ps/2 device are supported simultaneously (e.g., a usb keyboard and a ps/2 mouse.) the mixed environment is supported by allowing the emulation software to control the ps/2 interface. control of this interface includes capturing i/o accesses to port 60h and 64h and also includes capture of interrupts from the ps/2 keyboard controller. irq1 and irq12 from the legacy keyboard controller are routed through the usbc. when externalirqen in hcecontrol is set, irq1 and irq12 from the legacy keyboard controller are blocked by the usbc and an
chapter 5 functional operations 137 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information emulation interrupt is generated instead. this allows the emulation software to capture data coming from the legacy controller and present it to the application through the emulated interface. gate a20 sequence the gate a20 sequence often occurs in dos applications, usually to enable a20. to reduce the number of smis caused by the gate a20 sequence, the usbc only generates an smi if the a20 sequence changes the state of gate a20. the gate a20 sequence is initiated with a write of d1h to port 64h. on detecting this write, the usbc will set the gatea20sequence bit in hcecontrol . it will capture the data byte in hceinput but will not set inputfull bit in hcestatus . when gatea20sequence is set, a write of a value to i/o port 60h that has bit 1 set to a value different than a20state in hcecontrol will cause set inputfull and cause an interrupt. an smi with inputfull and gatea20sequence both set indicates that the application is trying to change the setting of gate a20 on the keyboard controller. however, when gatea20sequence is set and a write of a value to i/o port 60h that has bit 1 set to the same value as a20state in hcecontrol is detected then no interrupt will occur. as mentioned above, a write to 64h of any value other than d1h will cause gatea20sequence to be cleared. if gatea20sequence is active and a value of ffh is written to port 64h, gatea20sequence is cleared but inputfull is not set. a write of any value other than d1h or ffh will cause inputfull to be set which will then cause an smi. a write of ffh to port 64h when gatea20sequence is not set will cause inputfull to be set. emulation registers four emulation registers are used to provide the legacy support. each of these registers is located on a 32-bit boundary. table 26. host controller registers offset register description 100h hcecontrol it is used to enable and control the emulation hardware and report various status information. 104h hceinput it is the emulation side of the legacy input buffer register. 108h hceoutput it is the emulation side of the legacy output buffer register where keyboard and mouse data is to be written by software. 10ch hcestatus it is the emulation side of the legacy status register.
138 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information three of the registers ( hcestatus , hceinput , hceoutput ) are accessible at i/o address 60h and 64h when emulation is enabled. reads and writes to the registers using i/o addresses have side effects as outlined in the following table. hceinput register i/o data that is written to ports 60h and 64h is captured in this register when emulation is enabled. this register can be read or written directly by accessing it with its memory address in the usbc ? s register space. when accessed directly with a memory cycle, reads and writes of this register have no side effects. hceoutput register the data placed in this register by the emulation software is returned when i/o port 60h is read and emulation is enabled. on a read of this location, the outputfull bit in hcestatus is set to 0. hcestatus register the contents of the hcestatus register is returned on an i/o read of port 64h when emulation is enabled. reads and writes of port 60h and writes to port 64h can cause changes in this register. emulation software can directly access this register through its memory address in the usbc register space. access of this register through its memory address produces no side effects. 5.15.2 system management activity monitoring usb activity is monitored by the system management block. four signals are generated by the usbc to allow this monitoring: bulk activity, control activity, isochronous activity, and interrupt activity. bulk activity, control activity, and isochronous activity will pulse every time a usb transaction of table 27. register side effects i/o address cycle type register contents accessed/modified side effects 60h in hceoutput in from port 60h will set outputfull in hcestatus to 0 60h out hceinput out to port 60h will set inputfull to 1 and cmddata to 0 in hcestatus . 64h in hcestatus in from port 64h returns current value of hcestatus with no other side effect 64h out hceinput out to port 64h will set inputfull and cmddata in hcestatus to 1.
chapter 5 functional operations 139 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the specific type occurs. interrupt activity will pulse only when interrupt data is transmitted or received and an ack is returned. this functionality is added to the interrupt activity pulse to eliminate the possibility of the usb appearing to be active when no usb data is being transmitted. usbc signaled suspend and resume during the suspend state the usbc ? s list processing and sof token generation are disabled. however, the usbc ? s remote wakeup logic must monitor usb wakeup activity. the framenumber field of hcfmnumber does not increment while the usbc is in the suspend state. suspend is entered following a software reset or by command from the host controller driver. while in suspend, the usbc can force a transition to the resume state due to a remote wakeup condition. this transition may conflict with the host controller driver initiating a transition to the reset state. if this situation occurs, the hcd-initiated transition to reset has priority. the host controller driver must wait 5 ms after transitioning to suspend before transitioning to the resume state . likewise, the usbc must wait 5 ms after entering suspend before generating a local wakeup event and forcing a transition to resume. following a software reset, the host controller driver may cause a transition to the operational state if the transition occurs no more than 1 ms from the transition into suspend. if the 1-ms period is violated, it is possible that devices on the bus will go into suspend. when in the resume state, the usbc forces resume signaling on the bus. while in resume, the usbc is responsible for propagating the usb resume signal to downstream ports as specified in the usb specification. the usbc ? s list processing and sof token generation are disabled while in resume. in addition, the framenumber field of hcfmnumber does not increment while the usbc is in the resume state. resume is only entered from suspend. the transition to resume can be initiated by the host controller driver or by a usb remote wakeup signaled by the root hub. the usbc is responsible for resolving state transition conflicts between the hardware wakeup and host controller driver initiated state transitions. the usb 12 mhz clocks are disabled in the suspend state. in this state no activity is enabled which means the usb clocks
14 0 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information are unused. once suspended and all activity requiring a clock completes the usbc ? s clock generator is suspended. the following events will prevent the stoppage or re-enable the clock: n host controller driver forces an exit of the suspend state. n a resumedetected event interrupt is generated. n a ls eop is active. n a port connect/disconnect event transition requires the clock to be timed or is in progress. n a port reset is active on any port. selective suspend and resume a port can be selectively suspended by issuing a setportsuspend command which sets portsuspendstatus. while suspended the port does not propagate any downstream traffic. the port can be awakened by any of the following methods: n a clearportsuspend command n an upstream j to k transition. n a j to se0 transition which results in a disconnect event (no resume). when the port is resumed, the port drives the resume signal downstream for 20 ms followed by a ls eop. the port waits an additional 3 ms during which it propagates all traffic and then sets portsuspendstatuschange and clears portsuspendstatus. a disconnect event at a selectively suspended port does not generate a resume pulse. it sets connectstatuschange and clears portsuspendstatus. if the usbc is globally suspended, while the port is selectively suspended, the port does not respond to the usbc ? s transition to global resume. however, a remote wakeup condition at the port will force a resume transition. device signaled resume a remote wakeup generates a resumedetected interrupt and a transition to the resume state. a remote wakeup is defined as follows: n a k-state (resume) at an enabled port. n port connect/disconnect detection and remotewakeup- enable is set.
chapter 5 functional operations 141 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information n a port resume is in progress at a selectively suspended port. upstream resume or connect/disconnect wakeup events are controlled at both the port and global level. the usbc combines a ports resumedetected and connectstatuschange (if enabled) and does three things: 1) generates a resumedetected interrupt. 2) forces a transition to the resume state. 3) resumes any remaining enabled ports. usb interrupts the interrupt output of the usb block is functionally ored into the pci input interrupt, pirqd#. this result is then routed to an isa interrupt via function 0, offset 56h. 5.16 programmable interrupt controller (pic) introduction the programmable interrupt controller (pic) functions as an overall manager in an interrupt driven system environment. it accepts request from the peripheral equipment, determines which of the incoming request is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the cpu based on its determination. many of the features described here are not used in the normal pc environment. however, these features are useful if the pc is used as an embedded controller, or in industrial applications. each peripheral device usually has a special program that is associated with its specific operational requirements; this is referred to as a interrupt service routine (isr). the pic after issuing an interrupt to the processor will return a vector during the interrupt acknowledge cycle intack. this vector ? points to the vector table which contains the address of the actual isr. the pic is equivalent to the original 8259a. it manages eight levels or request. the AMD-756 controller contains two pics for a total of 16 interrupts. some of the channels are programmed by the bios for the standard peripherals. the other channels are programmed by the specific device drivers as they are loaded. the pics can be configured in fixed or rotating priority modes. in a pc they are normally set to fixed priority. if rotating priority is selected the channel being
142 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information serviced becomes the lowest priority. this prevents one channel from monopolizing the cpu. the priority mode can be changed dynamically. the interrupt request register (irr) and in-service register (isr) the interrupts at the ir input lines are handled by the two registers in cascade, the interrupt request register and the in- service register. the irr is used to store all the interrupt levels which are requesting service, and the isr is used to store all the interrupt levels being serviced. priority resolver this logic block determines the priority of the various bits set in the irr. the highest priority is selected and strobed into the corresponding bit of the isr during the intack cycle. interrupt mask register the imr stores the bits which mask the corresponding interrupt bit in the irr. the mask bits will not prevent an irr bit from being set. it does prevent that irr bit from generating an interrupt to the processor. if an irr bit is set and the channel mask bit is cleared, an interrupt will occur immediately.
chapter 5 functional operations 143 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information read/write control logic this block interfaces with the pci bus control signals. it also contains the operation command word (ocw) and the initialization command word (icw) registers which store the various control formats. the cascade buffer/comparator this function block stores and compares the id ? s of all the pic ? s used in the system. the associated three signals (cas[2:0]) are outputs when the pic is used as a master and are inputs when the pic is used as a target. as a master, the pic sends the id of the interrupting target device onto the internal cas[2:0] lines. the target will then send it ? s preprogrammed subroutine address onto the selected data bus during the two consecutive inta pulses. (see section ? cascading the pic ? .) interrupt sequence the powerful features of the pic in a computer are it's programmability and the interrupt routine addressing capability. the latter allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices. the normal sequence of events during an interrupt: 1. one or more of the interrupt request lines transition setting the appropriate irr bit(s). 2. the pic evaluates these request and asserts int to the cpu, if enabled and the channel is not masked. 3. the cpu responds with two interrupt acknowledge cycles. 4. on the first cycle the state of the irr bits is frozen for priority resolution. the highest priority isr bit is set, and the corresponding irr bit is reset. the master pic also issues the interrupt code on the cas[2:0] signals at the end of the first intack cycle. 5. on the second intack cycle the pic returns an 8 bit vector (pointer). this vector serves as an index into the interrupt vector table. 6. in the aeoi mode, the isr bit is reset at the end of the second intack cycle. otherwise the isr remains set until a eoi command is issued at the end of the interrupt subroutine.
144 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information if no interrupt request is present during the first intack cycle, the request was to short (a glitch). the pic will issue an interrupt level 7. figure 32. fpic block diagram data bus buffer read write logic cascade buffer/ comparator isr priority irr resolver control logic imr int cas[2:0] ir0 ir7 ad[7:0] table 28. interrupt vector byte contents d7 d6 d5 d4 d3 d2 d1 d0 ir7 t7t6t5t4t3 1 1 1 ir6 t7t6t5t4t3 1 1 0 ir5 t7t6t5t4t3 1 0 1 ir4 t7t6t5t4t3 1 0 0 ir3 t7t6t5t4t3 0 1 1 ir2 t7t6t5t4t3 0 1 0 ir1 t7t6t5t4t3 0 0 1 ir0 t7t6t5t4t3 0 0 0
chapter 5 functional operations 145 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.16.1 programming the pic accepts two types of command words. initialization command words (icws) these occur prior to normal operation. each pic must be brought to a starting point. whenever a write to icw1 occurs the following sequence begins: the edge sensitive circuit is reset. this means a low-to- high transition must occur to set the irr bits. the interrupt mask register is cleared. ir7 is assigned priority 7. the target mode address is set to 7. special mask mode is cleared and status read points to the irr. if bit ic4 in icw1 is 0. then all functions in icw4 are set to 0. non-buffered mode, no auto-eoi. operational command words (ocws) these command the pic to operate in a particular mode. they can be written anytime after the pic has been initialized. n fully nested n rotating priority n special masked mode n polled mode see section 7.4.4 on page 195 for icw bit definitions. icw1 vector and control this register contains the three least significant bits of the interrupt vector based on the interrupt level in service. ltim = 1 selects level-triggered mode. 0 = edge-triggered mode. adi = 1 interval equals 4 0 interval equals 8 sngl = 1 means one pic in the system; 0 means more than one. ic4 = if set then icw4 must be read. 0 means icw4 is not needed
146 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information icw2 interrupt vector the register contains the 5 most significant bits t[7:3] of the interrupt vector. icw3 icw3 is used when there are multiple pics. a) in the master mode a 1 is set for each target in the system. b) in the target mode bits 2:0 identify the target icw4 sfnm = 1 selects the special fully nested mode buf =1 selects the buffered mode m/s =1 means a master; 0 means a target if buf=1. if buf = 0 this bit has no meaning. aeoi =1 selects the automatic end of interrupt mode. upm =1 selects the 8086 mode of operation. figure 33. pic initialization sequence icw1 icw2 cascade mode ye s no (sngl=1) icw3 is icw4 needed? yes icw4=1 icw4 ready no (ic4=0)
chapter 5 functional operations 147 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information ocw1 interrupt mask register. each bit in this register will mask the corresponding irr bit. ocw2 ocw2 contains r,sl,eoi. these three bits control the priority rotation, and end of interrupt modes. ocw3 read register command and mask mode selection esmm = 1 enables special mask mode smm = 1 and esmm = 1 allows the pic to enter special mask mode. if smm = 0 the pic reverts to normal masked mode. if esmm is 0 this bit has no effect. fully-nested mode this mode is entered after initialization unless another mode is programmed. the interrupt request are ordered in priority from 0 to 7 (0 is the highest). when an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. additionally a bit in the interrupt service register is set. this bit remains set until the processor issues an eoi command before returning from the isr., or if aeoi is set, it is cleared at the end of the second intack cycle. while the is bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate an interrupt. these interrupts will only be acknowledged if the cpu has re-enabled its internal interrupt enable bit. in this fashion the programmer can control if he wishes to allow nested interrupts. after the initialization sequence, ir0 has the highest priority and ir7 has the lowest. priorities can be changed if rotating priority mode is selected. end of interrupt (eoi) the is bit can be reset either automatically following the trailing edge of the last intack cycle (if aeoi in icw1 is set), or by a reset eoi command from the cpu prior to returning from the isr. an eoi command must be issued twice when in cascade mode, once for the master and once for the target. there are two forms of eoi commands: specific and non- specific. when the pic operates in modes which preserve the fully nested structure, it can determine which is bit to reset on eoi. when a non-specific eoi command is issued, the pic will automatically reset the highest is of those that are set., since in the fully nested mode, the highest is level has to have been the
148 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information one serviced. a non-specific eoi can be issued when ocw2 (eoi=1, sl=0, and r=0). when a mode is used which may disturb the fully nested structure, the pic may no longer be able to determine the last level acknowledged. in this case, a specific eoi must be issued which includes as part of the command the is level to reset. a specific eoi can be issued when ocw2 (eoi=1, sl=1,r=0, and l0-2 is the binary level of the is bit to reset. take note that an is bit that is masked by an imr bit will not be cleared by a non-specific eoi if the pic is in the special masked mode. automatic end of interrupt (aeoi) mode if aeoi=1 in icw4, then the pic will operate in the aeoi mode. in this mode the pic automatically performs a non- specific eoi at the end of the second intack cycle. note, from a system perspective this mode should only be used when a nested multilevel interrupt structure is not required with in a single pic. aeoi can only be used in a master pic not in the target. priority rotation in some applications there are a number of interrupting devices. it may be desirable to give each device a fair share of the processor ? s time. when the pic is in the rotating mode a channel becomes the lowest priority after it is serviced. thus a device requesting service will have to wait, in the worst case, until each of the 7 other devices get serviced. there are two ways to accomplish automatic rotation using ocw2: the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode, which is set by (r=1, sl=0, eoi=0) and cleared by (r=0, sl=0, and eoi=0). specific priority the programmer can change priorities by programming the bottom priority and thus fixing the other priorities relative to it. i.e., if ir5 is programmed as the bottom priority, then ir6 will be the highest (ir5, ir4, ir3, ir2, ir1, ir0, ir7, ir6). the set priority command is issued in ocw2 (r=1, sl=1), and l[2:0] is the binary priority level code of the bottom choice. in this mode internal status is updated by software control during ocw2 writes. however, these updates are independent
chapter 5 functional operations 149 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocwr2 (r=1, sl=1, eoi=1) and l[2:0] = ir level to receive the lowest priority. interrupt mask each interrupt request input can be masked individually by the interrupt mask register (imr) programmed through ocw1. each bit in the imr mask the corresponding bit in the irr if set to 1. masking one ir channel does not affect the other channels. special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution. for example, the isr may wish to inhibit lower priority request for a portion of its execution but enable them for another portion. care must be taken to avoid inhibiting interrupts permanently. for example if an interrupt request is acknowledged and an eoi command did not reset its is bit the pic will inhibit all lower priority request with no easy way to re-enable them. this is where the special mask mode comes in. in the special masked mode, when a mask bit is set in ocw1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked.
150 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 34. priority cell poll command in this mode the int output is issued by setting p=1 in ocw3. the pic treats the next read as an interrupt acknowledge, set the appropriate is bit if there is a request pending and reads the priority level. the interrupt level is frozen between the write and the read. this mode is useful if there is a routine command common to several levels so that the intack sequence is not needed. another application is to use the poll mode to expand the number of priority levels. clr set q d cp q clr set q d cp q clr set q d cp q clr set q d cp q ltim bit 0= edge 1= level edge sense latch mask latch request latch master clear these lines go to other priority cells read irr freeze write mask read isr read imr inservice latch
chapter 5 functional operations 151 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information i equals 1 if there is an interrupt w[2:0] binary code of the highest priority requesting service. reading the pic status the input status of several internal registers can be read to give the programmer complete information on the status of the devices. the following registers can be read via ocw3: irr, isr, and imr (ocw1). to read the irr a read register command is written to ocw3 (rr=1, ris=0). to read the isr a read register command is written to ocw3 (rr=1, ris=1). there is no need to write an ocw3 before every status read operation, as long as the status read corresponds with the previous one; i.e., the pic remembers whether the irr or isr was previously selected by ocw3. this is not true when poll mode is used. after initialization the pic points to the irr. to read the imr, no ocw3 write is needed. just read ocw1. polling will override status reads when p=1 and rr=1 in ocw3. edge-triggered and level-triggered modes this mode is programmed using bit 3 in icw1. if ltim =0, an interrupt is recognized by a low-to-high transition on an ir input. the ir input must remain high until the intack is received. the ir input can remain high without generating another input. if ltim =1, an interrupt is recognized by a high level on an ir input and there is no need for a level change. the ir input must be removed before the eoi command is issued to prevent generating a second interrupt. the priority cell diagram shows a conceptual circuit of the level sensitive and edge sensitive circuitry. note that the request is a transparent latch. table 29. polling status format i----w2w1w0
152 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information in both edge and level triggered modes, the ir inputs must remain high until after the falling edge of the first intack cycles. if the ir input goes low before this time, a default ir7 vector will be returned. this can be used as a safeguard for detecting interrupts caused by spurious noise glitches on the ir pins. to implement this feature the ir7 routine is used for clean up simply execute a return instruction, thus ignoring the interrupt. if ir7 is used for a device a default ir7 can still be detected by reading the isr. if high it was a real interrupt. if low it was noise. special full-nested mode this mode is used in the case of a large system where cascading is used and the priority has to be preserved in each target. in this case the master is programmed to the fully nested mode (icw4). this mode is similar to the normal nested mode with the following exceptions: 1. when an interrupt request from a certain target is in service, this target is not locked out from the master ? s priority logic, and further interrupt request from higher priority ir ? s within the target will be recognized by the master and initiate interrupts to the processor. (in normal nested mode, a target is masked out when its request is in service and no higher request from the target can be serviced.) 2. when exiting the interrupt service routine, the software must check whether the interrupt serviced was the only one from that target by sending a non-specific eoi command to the target and then reading its in-service register and checking for zero. if it is empty, a non-specific eoi can be sent to the master also. if not, no eoi should be sent. buffered mode this mode of the original 82c59a is not supported. cascade mode the original 82c59a could be interconnected to support up to 8 targets for a total of 64 priority levels. the pic only supports up to 16 priority levels. the master pic controls the target through the 3 internal cascade signals. since these signals are not available on external pins no further cascading is possible. each pic in the system must follow a separate initialization sequence and can be programmed to work in a different mode. an eoi command must be issued twice: once for the master and once for the target.
chapter 5 functional operations 153 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5.17 i/o advanced programmable interrupt controller (ioapic) introduction the AMD-756 peripheral bus controller incorporates an i/o advanced programmable interrupt controller (apic) in addition to the pic. the apic architecture is one of several mechanisms required for improving the multiprocessor performance of amd athlon processors. the apic allows interrupt-related traffic to be offloaded from the memory bus, which makes memory more available for processor use. in addition, the apic dedicated interrupt bus can provide an advantage in single processor systems, by reducing the interrupt latency associated with the propagation of interrupt-acknowledge cycles over multiple buses. the apic controller architecture consists of two components ? a local apic and an ioapic. figure shows a system-level implementation of the apic components. the local apic and ioapic communicate over the interrupt message bus (imb). local apic the local apic processes interrupts generated by local i/o devices, by software, and by the programmable timer. in addition, it processes interrupts communicated on the imb, by the i/o devices connected to the ioapic, and by another processor ? s local apic (inter-processor interrupts). the local apic communicates these local and external interrupts to the processor. in addition, the local apic is responsible for the nesting, queueing, and masking of interrupts. the local apic can be implemented as a discrete component or integrated with the processor. the amd athlon processor integrates the local apic. ioapic the ioapic consists of 24 incoming interrupts, a 24-entry redirection table, several programmable registers, and an imb unit for interfacing with the imb as shown in figure 35. each of the incoming interrupts has a corresponding entry in the redirection table. the entry is programmed with edge/level sensitivity, interrupt vector, priority, the destination processor, and whether the processor is selected statically or dynamically. when an incoming interrupt is asserted, the ioapic uses the information programmed in the redirection table entry to format the interrupt message to be communicated on the imb.
154 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 35. system-level implementation of apic components write snoop capable input before sending an interrupt message, the AMD-756 peripheral bus controller waits for an acknowledge signal (wsc#), which indicates that the apic can send the interrupt message. the wsc# signal connects between the AMD-756 and the amd-751 system controller and is used to confirm that, before an interrupt message is sent across the imb, the most recent pci bus cycles that write data to system memory have been placed in ? coherent ? memory space. in general, interrupt lines (irqs) can be activated when a device finishes sending data across the pci bus. however, there is a possibility that the data is not accessible to the processor before the interrupt service routine attempts to access it. to avoid this possibility, the ioapic does not send an interrupt message on the imb until it receives confirmation that all data in the amd-751 buffers has made it to coherent space. the AMD-756 peripheral bus controller requests that the amd-751 system controller issue a fence command to its amd-751 ? system controller amd athlon ? processor pci bus AMD-756 ? peripheral bus controller i/o apic local apic local interrupts local apic amd athlon ? processor imb bus smi reset lint1 lint0 wsc#
chapter 5 functional operations 155 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information buffers by placing a single pclk pulse on wsc#. the amd-751 system controller then marks the data currently in its buffers and waits for this data to reach processor-accessible space. when this data reaches processor-accessible space, the amd-751 responds by sending a two-clock pulse back to the AMD-756 peripheral bus controller. after this pulse is received, the AMD-756 transmits the interrupt message over the imb. figure 36. wsc# timing interrupt message bus (imb) the local apics and the ioapics communicate via the three-line synchronous interrupt message bus (imb). two of these lines (picd0 and picd1) are used for data transmission and the third line (piclk) is a clock. in addition, picd0 is used for arbitration. arbitration a rotating priority arbitration protocol is used to gain access to the bus and send an interrupt message. after reset, each apic is assigned an arbitration priority of 0 to 15. the arbitration priority is loaded with the value of the arbitration id after reset. before sending a message, each apic presents the type of message it is sending and its current arbitration priority on the apic bus. the message types are eoi message, which is a high-priority message, and normal message, which can be either a short message or a nonfocused lowest-priority message. because the eoi message is the highest-priority message, it is granted the bus regardless of the arbitration priority of the sender. if the message is a normal message, the apic with the highest priority wins the arbitration and sends the message. after the message has been successfully sent, all apics increment their priority by 1. the apic whose priority was 15 takes the winners arbitration priority. pclk message sent request to send wsc# imb
156 functional operations chapter 5 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 6 initialization 157 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 6 initialization all programmable features in the AMD-756 peripheral bus controller are controlled by the pci configuration registers, which are normally programmed only during system initialization. this chapter summarizes the register functions, default values, access types, and addresses. for more detailed descriptions of the configuration registers, see chapter 7 on page 169. access types are indicated as follows: rw read/write ro read only wo write only rwc read, write 1 ? s to clear individual bits
158 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 6.1 legacy i/o registers table 30. slave dma controller registers port register name access 00h ch 0 base/current address rw 01h ch 0 base/current count rw 02h ch 1 base/current address rw 03h ch 1 base/current count rw 04h ch 2 base/current address rw 05h ch 2 base/current count rw 06h ch 3 base/current address rw 07h ch 3 base/current count rw 08h status/command rw 09h write request wo 0ah write single mask wo 0bh write mode wo 0ch clear byte pointer f/f wo 0dh master clear wo 0eh clear mask wo 0fh r/w all mask bits rw table 31. master interrupt controller registers port register name access 20h master interrupt control note 1 21h master interrupt mask note 1 20h master interrupt control shadow rw 21h master interrupt mask shadow rw note: 1. rw if shadow registers are disabled table 32. timer/counter registers port register name access 40h timer/counter 0 rw 41h timer/counter 1 rw 42h timer/counter 2 rw 43h timer/counter control wo
chapter 6 initialization 159 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 33. keyboard controller registers port register name access 60h keyboard controller data rw 61h misc. functions and speaker control rw 64h keyboard controller command/status rw table 34. cmos/rtc/nmi registers port register name access 70h cmos memory address & nmi disable wo 71h cmos memory data (128 bytes) rw 72h cmos memory address rw 73h cmos memory data (256 bytes) rw 74h cmos memory address rw 75h cmos memory data (256 bytes) rw table 35. dma page registers port register name access 87h dma page ? dma channel 0 rw 83h dma page ? dma channel 1 rw 81h dma page ? dma channel 2 rw 82h dma page ? dma channel 3 rw 8fh dma page ? dma channel 4 rw 8bh dma page ? dma channel 5 rw 89h dma page ? dma channel 6 rw 8ah dma page ? dma channel 7 rw table 36. system control registers port register name access 92h system control rw
16 0 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 37. slave interrupt controller registers port register name access a0h slave interrupt control note 1 a1h slave interrupt mask note 1 a0h slave interrupt control shadow rw a1h slave interrupt mask shadow rw note: 1. rw if shadow registers are disabled table 38. master dma controller registers port register name access c0h ch 0 base/current address rw c2h ch 0 base/current count rw c4h ch 1 base/current address rw c6h ch 1 base/current count rw c8h ch 2 base/current address rw cah ch 2 base/current count rw cch ch 3 base/current address rw ceh ch 3 base/current count rw d0h status/command rw d2h write request wo d4h write single mask wo d6h write mode wo d8h clear byte pointer f/f wo dah master clear wo dch clear mask wo deh r/w all mask bits rw table 39. miscellaneous control port register name access 0f1h - 0f0h cpu reset/ferr clear rw table 40. interrupt controller level select port register name access 04d1h - 04d0h level sensitive irq select rw
chapter 6 initialization 161 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 41. pci control port register name access 0cfbh - 0cf8h pci address rw 0cffh - 0cfch pci data rw table 42. configuration space pci-to-isa header registers offset pci header default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 7408h ro 05h ? 04h command 000fh rw 07h ? 06h status 0200h rwc 08h revision id (01h = rev a) 01h ro 09h program interface 00h ro 0ah sub class code 01h ro 0bh base class code 06h ro 0ch reserved (cache line size) -- ? 0dh reserved (latency timer) -- ? 0eh header type 80h ro 0fh built-in self test (bist) 00h ro 2dh-2ch bridge subsystem vendor id 0000h ro 2fh-2eh bridge subsystem id 0000h ro 10h ? 3fh reserved -- ? table 43. isa bus control registers offset register default recommended access setting result 40h isa bus control 1 00h 00h normal isa timing rw 41h isa bus control 2 00h 01h refresh mode rw
162 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 42h reserved 43h rom decode control 00h 00h romcs# f0000h- fffffh rw 44h keyboard controller control 00h 01h disable mouse lock rw 45h type f dma control 00h 00h set dma type f if needed rw 46h miscellaneous control 1 00h 00h disable post memory write rw 47h miscellaneous control 2 00h c0h init as cpu reset enable pci delay transaction rw 48h miscellaneous control 3 01h 01h enable usb, ide rw 49h miscellaneous control 4 08h 08h isa bus to be 12 milliamps ? 4ah ide interrupt routing 84h 84h wait for pgnt before grant to isa master/dma ide primary channel irq14 secondary channel irq 15 rw 4bh ioapic configuration register 00-- 00-- accesses to ioapic are disabled ? 4ch dma/master mem access ctrl 1 00h 00h pci memory hole bottom address ha23 ? ha16 = 0 rw 4dh dma/master mem access ctrl 2 00h 00h pci memory hole top address ha23 ? ha16 = 0 rw 4f-4eh dma/master mem access ctrl 3 0300h f300h top of pci memory for isa=16m. forward 00000h-9ffffh access to pci rw 52h-50h bridge subsystem vendor id 0000h value placed is accessed via 2dh-2ch rw 54h-52hh bridge subsystem id 0000h value placed is accessed via 2fh- 2eh rw table 43. isa bus control registers (continued) offset register default recommended access setting result
chapter 6 initialization 163 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 44. distributed dma offset register default recommended access setting result 61h ? 60h channel 0 base address/enable 0000h 0000h disabled rw 63h ? 62h channel 1base address/enable 0000h 0000h disabled rw 65h ? 64h channel 2 base address/enable 0000h 0000h disabled rw 67h ? 66h channel 3 base address/enable 0000h 0000h disabled rw 69h ? 68h reserved -- ? disabled ? 6bh ? 6ah channel 5 base address/enable 0000h 0000h disabled rw 6dh ? 6ch channel 6 base address/enable 0000h 0000h disabled rw 6fh ? 6eh channel 7 base address/enable 0000h 0000h disabled rw 71h-70h device and subsystem id rw 0000h 0000h ro ffh ? 72h reserved -- ??
164 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 6.2 pci function 1 registers ? ide controller table 45. configuration space ide header registers offset pci header default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 7409h ro 05h ? 04h command 0080h rw 07h ? 06h status 0280h rw 08h revision id 02h ro 09h program interface 8ah rw 0ah sub class code 01h ro 0bh base class code 01h ro 0ch reserved (cache line size) 00h ? 0dh latency timer 00h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 13h ? 10h base address ? primary data/command 0000_01f1h rw 17 h ? 14h base address ? primary control/status 0000_03f5h rw 1bh ? 18h base address ? secondary data/command 0000_0171h rw 1fh ? 1ch base address ? secondary control/status 0000_0375h rw 23h ? 20h base address ? bus master control 0000_cc01h rw 2fh ? 24h reserved (unassigned) -- ? 33h ? 30h reserved (expansion rom base address) -- ? 3bh ? 34h reserved (unassigned) -- ? 3ch interrupt lines 00h rw/ro 3dh interrupt pin 01h ro 3eh minimum grant 00h ro 3fh maximum latency 00h ro
chapter 6 initialization 165 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 46. configuration space ide registers offset register default recommended access setting result 40h chip enable 00h 03h enable pri and sec channel rw 41h ide configuration 002h e0h enable pri and sec read prefetch buffer enable pri post write buffer rw 47h-42h reserved (do not program) -- -- -- 4bh ? 48h drive timing control a8a8a8a8h a8a8a8a8h dior# and diow# pulse width set to 11 pci clocks recovery time set to 9 clocks rw 4ch address setup time ffh ffh address setup time 4t rw 4dh reserved (do not program) -- -- -- 4eh sec non-1f0h port access timing ffh ffh sec non-1f0 port access, dior# and diow# pulse width set to 17 pci clocks rw 4fh pri non-1f0h port access timing ffh ffh pri non-1f0 port access, dior# and diow# pulse width set to 17 pci clocks rw 53h ? 50h ultra dma33 extended timing control 03030303h 03030303h pri and sec drive 0 and 1mode enabled by set feature command disabled ultra dma33 mode rw 57h-54h reserved -- ?? 5fh ? 58h reserved -- -- ? 61h ? 60h reserved -- -- ? 67h ? 62h reserved -- ?? 69h ? 68h reserved -- -- ? 6ah ? ffh reserved -- -- ?
16 6 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 6.3 pci function 3 registers ? power management 6.3.1 power management configuration space registers table 47. ide controller i/o registers offset register name default access 00h primary channel command 00h rw 01h reserved -- ? 02h primary channel status 00h rwc 03h reserved -- ? 07h ? 04h primary channel prd table address 00h rw 08h secondary channel command 00h rw 09h reserved -- ? 0ah secondary channel status 00h rwc 0bh reserved -- ? 0fh ? 0ch secondary channel prd table address 00h rw table 48. configuration space power management header registers offset pci header default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 7403h ro 05h ? 04h command 0000h rw 07h ? 06h status 0280h rwc 08h revision id 01h ro 09h program interface 00h ro 0ah sub class code 00h ro 0bh base class code 00h ro 0ch cache line size 00h ro 0dh latency timer 16h rw 0eh header type 00h ro
chapter 6 initialization 167 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 49. configuration space power management registers offset register default recommended access setting result 41h general configuration 40h 40h enable acpi timer reset acpi 24-bit timer count 32us clock throttling rw 42h sci interrupt configuration 00h 00h disable sci interrupt rw 43h most previous power state 00h 00h rw 45h ? 44h pnp irq select 0000h 0000h disable pri interrupt channel rw 47h ? 46h pnp dma and chip select 0000h 0000h disable sec interrupt channel rw 48h reset strap options xxh -- enable int rtc, ps2 mouse, int kbc rw 4ah serial irq control 10h 10h 6 start clocks rw 4ch prdy timer control 00h 00h enables counters rw 4eh square wave generation 00h 00h disable square wave rw 53h ? 50h power state pin control 0000_0000h 0000_0000h disable power management rw
16 8 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 5bh-58h system management i/o space pointer 0000_dd01h 0000_dd01h system management i/o base rw 5fh-5ch reserved -- -- -- 63h-60h system management class code write 0000_0000h 0000_0000h value to be returned by register at offset 08h (classcode) rw a3h-a0h serial port trap address register 0278_03f8h 0278_03f8 the following trap and mask registers can be used to generate and smi or sci, load the associated re-trigger timers, load the system inactivity timers or load the burst timers rw a5h-a4h serial port trap mask register 0f0fh 0f0fh rw abh-a8h audio port 1 and 2 trap address 0330_0220h 0330_0220h rw afh-ach audio port 3 and 4 trap address 0338_0530h 0338_0530h rw b3h-b0h audio port trap mask register 0707_010fh 0707_010fh rw b7h-b4h pcmcia trap 1 and 2 i/o address register 0000_0000h 0000_0000h rw bbh-b8h pcmcia trap 1 memory address register 0000_0000h 0000_0000h rw bfh-bch pcmcia trap 2 memory address register 0000_0000h 0000_0000h rw c3h-c0h pcmcia trap mask register 0000_0000h 0000_0000h rw c7h-c4h programmable i/o range monitor 1 through 4 trap address register 0000_0000h 0000_0000h rw cbh-c8h programmable i/o range monitor 3 and 4 trap address 0000_0000h 0000_0000h rw cfh-cch programmable i/o monitor trap mask register 0000_0000h 0000_0000h rw d3h-d0h programmable memory range monitor 1 trap address 0000_0000h 0000_0000h rw d7h-d4h programmable memory range monitor 2 trap address 0000_0000h 0000_0000h rw dbh-d8h programmable memory range monitor trap mask address 0000_0000h 0000_0000h rw table 49. configuration space power management registers (continued) offset register default recommended access setting result
chapter 6 initialization 169 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 6.3.2 power management i/o space registers table 50. basic power management control/status registers offset register name default access 01h ? 00h power management 1 status 00h rwc 03h ? 02h power management 1 enable 00h rw 05h ? 04h power management 1 control 00h rw 0bh ? 08h power management 1 timer 00h rw table 51. processor power management registers offset register name default access 13h ? 10h processor control 0000h rw 14h processor level 2 00h ro 15h processor level 3 00h ro 17h-16h resume event enable 0000h rw 19h-18h flag write 0000h rw 1bh-1ah flag read 0000h ro 1ch soft logic test 00h rw table 52. general purpose power management registers offset register name default access 23h ? 22h acpi interrupt enable 00h rw 24h lpt-usb event status 00h rw 25h lpt-usb event interrupt enable 00h rw 27h ? 26h power supply control 2200h rw table 53. generic power management registers offset register name default access 29h ? 28h global status 0000h rwc 2bh ? 2ah global smi enable 0000h rw 2dh ? 2ch global smi control 0000h rw 2fh software smi command 00h rw 94h-40h reserved -- -- 9bh ? 98h system inactivity timer 0000_0000h rw a7h-a0h reserved -- -- abh-a8h hardware trap status register 0000_0000h rw afh-ach hardware trap enable 0000_0000h rw
170 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information b3h-b0h hardware trap reload enable timer 0000_0000h rw b7h-b4h irq reload enable system inactivity timer 0000_0000h rw d1h-c0h general purpose i/o pins gpio select rw d7h-d4h gpio pin interrupt status 0000_0000h rw dbh-d8h gpio pin interrupt enable 0000_0000h rw dfh-dch gpio output clock 0 and 1 ffff_ffffh rw e1h-e0h smbus global status 0000h rw e3h-e2h smbus global control 0000h rw e5h-e4h smbus host address 0000h rw e7h-e6h smbus host data 0000h rw e8h smbus host command field 00h rw e9h smbus host block datafifo access 00h rw ebh-eah smbus host-as-slave data 0000h ro edh-ech smbus host-as-slave device address 0000h ro eeh smbus host-as-slave host address 00h rw efh smbus snoop address 00h rw table 53. generic power management registers (continued) offset register name default access
chapter 6 initialization 171 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 6.4 pci function 4 registers ? usb controller table 54. configuration space usb header registers offset pci header default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 740ch ro 05h ? 04h command 0000h rw 07h ? 06h status 0280h rwc 08h revision id (00h = first silicon) 06h ro 09h program interface 10h ro 0ah sub class code 03h ro 0bh base class code 0ch ro 0ch cache line size 00h ro 0dh latency timer 10h rw 0eh header type 00h ro 0fh built-in self test (bist) 00h ro 13h-10h base address 0000_0000h rw 1fh ? 14h reserved ?? 23h ? 20h i/o register base address 0000_0001h rw 3bh ? 24h reserved 00h ? 3ch interrupt line register 00h rw 3dh interrupt pin register 04h ro 3eh min_gnt 00h ro 3fh max_gnt 50h ro 44h operational mode enable 00h rw table 55. usb controller i/o registers offset register name default access 03h ? 00h hcrevision 0000_0110h r 07h-04h hccontrol 0000_0600h rw 0bh-08h hccommandstatus 0000_0000h rw 0fh-0ch hcinterruptstatus 0000_0000h rw 13h-10h hcinterruptenable 0000_0000h rw 17h-14h hcinterruptdisable 0000_0000h rw 1bh-18h hchcca 0000_0000h rw
17 2 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 6.4.1 pins latched at the trailing edge of reset each of the following pins is latched at the trailing edge of a reset signal to specify a configuration. to latch a low, these pins are tied to ground through a 10-kohm resistor. to latch a high, these pins are connected to the appropriate power plane through a 10-kohm resistor. each of these latches is accessible in function 3, offset 48 and can be modified if needed. daddrf[2:0], dcs1f# these pins are latched at the trailing edge of pwrgd reset and read-write accessible via function 3, offset 48 bits[9:6]. the output of the pins is also read accessible from the keyboard 1fh-1ch hcperiodcurrented 0000_0000h rw 23h-20h hccontrolheaded 0000_0000h rw 27h-24h hccontrolcurrented 0000_0000h rw 2bh-28h hcbulkheaded 0000_0000h rw 2fh-2ch hcbulkcurrented 0000_0000h rw 33h-30h hcdonehead 0000_0000h rw 37h-34h hcfminterval 0000_2edf rw 3bh-38h hcframeremaining 0000_0000h rw 3fh-3ch hcfmnumber 0000_0000h rw 43h-40h hcperiodstart 0000_0000h rw 47h-44h hclsthresold 0000_0628h rw 4bh-48h hcrhdescriptora 0100_0004h rw 4fh-4ch hcrhdescriptorb 0000_0000h rw 53h-50h hcrhstatus 0000_0000h rw 57h-54h hcrhportstatus[1] 0000_0000h rw 5bh-58h hcrhportstatus[2] 0000_0000h rw 5f-5ch hcrhportstatus[3] 0000_0000h rw 63-60h hcrhportstatus[4] 0000_0000h rw 100h hcecontrol 0000_0000h rw 104h hceinput 0000_00xxh rw 108h hceoutput 0000_00xxh rw 10ch hcestatus 0000_0000 rw table 55. usb controller i/o registers (continued) offset register name default access
chapter 6 initialization 17 3 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information controller registers. these bits are mapped to the keyboard controller register bits as shown in table 56. rom_kbcs# this is the internal keyboard controller enable is latched at the trailing edge of pwrgd reset. when high, the internal keyboard is selected. when low, the external keyboard is selected. see the keyboard controller section of the pin descriptions to see how this affects the keyboard pin functions. table 56. keyboard controller register bit mapping pin keyboard controller register bit daddrp[2] rp[16] daddrp[1] rp[15] daddrp[0] rp[14] dcs1p# rp[13]
174 initialization chapter 6 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 7 registers 17 5 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7 registers this section describes the AMD-756 peripheral bus controller configuration and i/o registers. 7.1 table conventions possible values for the default state after reset are: n 0 n 1 n x the value is indeterminate n d the value is programming dependent, and the value is discussed in the bit article possible values for the access type are: n rw read/write n ro read only n wo write only n rwc write 1 to the bit to clear it if a bit ? s value is 1, it said to be set (or high). setting a bit means to make it 1. if a bit ? s value is 0, it is said to be cleared (or low). clearing a bit means to make it 0. reserved bits should be read as 0, unless otherwise noted. 7.2 pci mechanism #1 registers in the AMD-756 peripheral bus controller are accessed through pci configuration mechanism #1, which is described in pci local bus specification revision 2.1 . it employs i/o locations 0cf8h to 0cfbh to specify the target address and locations 0cfch to 0cffh for data to the target address. these registers are located in the amd-751 system controller.
176 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information the target address includes the specific pci bus, device, function number, and register number within a pci device. the amd-751 system controller uses the device number to assert one of the ad[23:16] address/data lines. access to the configuration address space of the AMD-756 peripheral bus controller requires device selection decoding to be done externally via the idsel signal, which functions as a chip select signal. the idsel signal associated with device number 0 is connected to ad16, idsel of device number 1 is connected to ad17, and so forth. the connection of the AMD-756 peripheral bus controller idsel is system-specific. pci configuration address ports 0cfbh ? 0cf8h bit name description default access type 31 en configuration space enable. 0 = i/o access passed on unchanged 1 = targeted pci device responds 0rw 30-24 reserved. always reads 0. 0 rw 23-16 busnum pci bus number. selects a specific system pci bus. 0rw 15-11 devnum device number. selects a specific system device. 0rw 10-8 f uncn um function number. selects the number of a specific function space in memory. 0rw 7-2 regnum register number. these bits, in conjunction with the pci byte enable lines c/be[3:0]#, specify the offset number of a register within the chosen function space. 0rw 1-0 reserved. always reads 0. 0 rw note: pci configuration address is a read/write port that responds only to doubleword accesses. byte or word accesses are passed on unchanged. pci configuration data ports 0cfch ? 0cffh bit name description default access type 31 data configuration data. xrw note: pci configuration data is a read/write port that responds only to doubleword accesses. byte or word accesses are passed on unchanged.
chapter 7 registers 17 7 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.3 register summaries the following tables (table 57 ? table 63) list all available registers that reside in the AMD-756 peripheral bus controller. the tables are in order by function number, and the table entries are in order by offset. table 57. pci-isa bridge configuration (function 0) offset function default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 7408h ro 05h ? 04h command 000fh rw 07h ? 06h status 0200h rwc 08h revision id 01h ro 09h program interface 00h ro 0ah sub class code 01h ro 0bh base class code 06h ro 0ch cache 00h ro 0dh latency timer 00h rw 0eh header type 80h ro 0fh bist 00h ro 2bh ? 10h reserved -- -- 2dh ? 2ch subsystem vendor id 0000h ro 2fh ? 2eh subsystem id 0000h ro 3fh ? 30h reserved -- -- 40h isa bus control 1 00h rw 41h isa bus control 2 00h rw 42h reserved 43h rom decode control 00h rw 44h reserved 45h type f dma control 00h rw 46h miscellaneous control 1 00h rw 47h miscellaneous control 2 00h rw 48h miscellaneous control 3 01h rw 49h miscellaneous control 4 08h rw 4ah ide interrupt routing 84h rw
178 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 4bh io apic configuration register 00h rw 4dh-4ch isa dma access control 1 0000h rw 4fh-4eh isa dma access control 3 0300h rw 53-50h device and subsystem id register 0000h rw 5fh ? 54h reserved -- -- 61h-60h distributed dma channel 0 0000h rw 63h-62h distributed dma channel 1 0000h rw 65h ? 64h distributed dma channel 2 0000h rw 67h-66h distributed dma channel 3 0000h rw 69h-68h reserved -- -- 6bh-6ah distributed dma channel 5 0000h rw 6dh-6ch distributed dma channel 6 0000h rw 6fh-6eh distributed dma channel 7 0000h rw ffh-70h subsystem vendor id 0000h rw table 57. pci-isa bridge configuration (function 0) (continued) offset function default access
chapter 7 registers 179 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 58. ide configuration (function 1) offset function default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id (ide1 device) 7409h ro 05h ? 04h command 0000h rw 07h ? 06h status 0200h rwc 08h revision id 01 ro 09h program interface 80h rw 0ah sub class code 01h ro 0bh base class code 01h ro 0ch reserved -- -- 0dh latency timer 00h rw 0eh header type 00h ro 0fh bist 00h ro 13h ? 10h base address 0 (bar0) primary data and command 0000_01f1h rw 17 h ? 14h base address 1(bar1) primary control and status 0000_03f5h rw 1bh ? 18h base address 2 (bar2) secondary data and command 0000_0171h rw 1fh-1ch base address 3 (bar3) secondary control and status 0000_0375h rw 23h-20h eide controller master control registers base address 0000_cc01h rw 3bh ? 24h reserved -- -- 3dh-3ch interrupt pin and line 000eh rw 3fh-3eh minimum grant and maximum latency 0000h ro 43h-40h ide configuration register 0000_0000h ro 47h-44h reserved 4bh-48h ide drive timing control a8a8_a8a8h rw 4fh-4ch cycle time and address setup time ffff_00ffh rw 53h-50h ultra dma timing control 0303_0303h rw 5fh ? 54h reserved -- -- ffh ? 6ch reserved -- --
18 0 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 59. power management configuration (function 3) offset function default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 740bh ro 05h ? 04h command 0000h rw 07h ? 06h status 0280h rwc 08h revision id nn ro 09h program interface 00h ro 0ah sub class code 00h ro 0bh base class code 00h ro 0ch cache 00h ro 0dh latency timer 16h rw 0eh header type 00h ro 0fh bist 00h ro 40h ? 10h reserved -- -- 41h general configuration 40h rw 42h sci interrupt configuration 00h rw 43h previous power state 00h ro 45h-44h pnp irq select 0000h rw 47h-46h pnp dma and chip select 0000h rw 49h-48h pins latch on reset 00xx_x100_ 00x0_x100b rw 4ah serial irq control 10h rw 4bh reserved -- -- 4ch prdy timer control 00h rw 4dh reserved -- -- 4eh square wave generator 00h rw 4fh reserved -- -- 53h-50h power state pin control 0000_0000h rw 54h pci ir edge/level select 00h rw 55h reserved -- -- 57h-56h pci irq routing register 0000 rw 5bh-58h system management i/o base (pm00) 0000_dd01h ro 5fh-5ch test 0000_0000h rw 63h-60h system management class code 0000_0000h rw 9fh ? 64h reserved -- --
chapter 7 registers 181 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information a3h ? a0h serial port trap address 02f8_03f8h ro a5h ? a4h serial port trap mask 0f0fh ro a7h ? a6h reserved -- -- abh ? a8h audio port 1 and 2 trap address 0330_0220h rw afh ? ach audio port 3 and 4 trap address 0338_0530h rw b3h ? b0h audio trap mask 0707_010fh rw b7h ? b4h pcmcia trap 1 and 2 i/o address 0000_0000h rw bbh ? b8h pcmcia trap 1 address 0000_0000h rw bfh ? bch pcmcia trap 2 address 0000_0000h rw c3h ? c0h pcmcia trap task 0000_0000h rw c7h ? c4h i/o range monitor 1 and 2 trap address 0000_0000h rw cbh ? c8h i/o range monitor 3 and 4 trap address 0000_0000h rw cfh ? cch i/o range monitor mask 0000_0000h rw d3h ? d0h memory range monitor 1 trap address 0000_0000h rw d7h ? d4h memory range monitor 2 trap address 0000_0000h rw dbh ? d8h memory range monitor trap mask 0000_0000h rw ffh ? dch reserved -- -- table 59. power management configuration (function 3) (continued) offset function default access
182 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 60. usb configuration (function 4) offset function default access 01h ? 00h vendor id 1022h ro 03h ? 02h device id 740ch ro 05h ? 04h command 0000h rw 07h ? 06h status 0280h rwc 08h revision id nn ro 09h program interface 10h ro 0ah sub class code 03h ro 0bh base class code 0ch ro 0ch cache 00h ro 0dh latency timer 10h r 0eh header type 00h ro 0fh bist 00h ro 13h ? 10h base address 0 (usb00) 0000_0000h rw 3bh ? 14h reserved -- -- 3ch interrupt line 00h rw 3dh interrupt pin 04h rw 3eh minimum grant 00h rw 3fh maximum latency 50h rw 43h ? 40h reserved -- -- 44h operational mode 00h rw ffh ? 45h reserved -- --
chapter 7 registers 183 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 61. enhanced ide (eide) i/o registers offset cache control default access 00h primary bus master command 00h rw 02h primary bus master status 00h rw 07h-04h primary bus master prd table address 0000_0000h rw 08h secondary bus master command 00h rw 0ah secondary bus master status 00h rw 0fh ? 0ch secondary bus master prd table address 0000_0000h rw note: the base pointer for the enhanced ide (eide) i/o registers is function 1, offset 20h.
184 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 62. usb open hci memory-mapped registers offset cache control default access 03h-00h hc revision 0000_0110h ro 07h-04h hc control 0000_0600h rw 0bh-08h hc command/status 0000_0000h rw 0fh-0ch hc interrupt status 0000_0000h rw 13h-10h hc interrupt enable 0000_0000h rw 17 h ? 14h hc interrupt disable 0000_0000h rw 1bh-18h hc hcca 0000_0000h rw 1fh ? 1ch hc period current ed 0000_0000h ro 23h ? 20h hc control head ed 0000_0000h rw 27h ? 24h hc control current ed 0000_0000h rw 2bh ? 28h hc bulk head ed 0000_0000h rw 2fh ? 2ch hc bulk current ed 0000_0000h rw 33h ? 30h hc done head 0000_0000h rw 37h ? 34h hc fm interval 0000_2edfh rw 3bh ? 38h hc frames remaining 0000_0000h ro 3fh ? 3ch hc fm number 0000_0000h rw 43h ? 40h hc period start 0000_0000h rw 47h ? 44h hc ls threshold 0000_0628h rw 4bh ? 48h hc rh descriptor a 0100_0004h rw,ro 4fh ? 4ch hc rh descriptor b 0000_0000h rw 53h ? 50h hc rh status 0000_0000h rwc,ro 57h ? 54h hc rh port status 1 0000_0000h rw 5bh ? 58h hc rh port status 2 0000_0000h rw 5fh ? 5ch hc rh port status 3 0000_0000h rw 63h ? 60h hc rh port status 4 0000_0000h rw 100h hce control 0000_0000h ro 104h hce input 0000_00xxh rw 108h hce output 0000_00xxh rw,ro 10ch hce status 0000_0000h rw note: the base pointer for the usb open hci memory-mapped registers is function 4, offset 10h.
chapter 7 registers 185 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 63. power management i/o-mapped registers offset function default access 01h ? 00h power management 1 status 0000h rwc 03h ? 02h power management 1 enable 0000h rw 05h ? 04h power management 1 control 0000h rw 0bh ? 08h acpi power management timer 0000_0000h ro 13h-10h cpu clock control 0000_0000h rw 14h processor level 2 00h ro 15h processor level 3 00h ro 17h-16h resume event enable 0000h rw 19h-18h flag write 0000h rw 1bh-1ah flag read 0000h rw 1ch soft logic test 00h rw 23h-22h acpi interrupt enable 0000h rw 24h lpt-usb event status 00h rw 25h lpt-usb event interrupt enable 00h rw 27h-26h power supply control 2200h rw 29h-28h global status register 0000h rw 2bh-2ah global smi enable 0000h rw 2dh-2ch global smi control 0000h rw 2fh software smi trigger 00h rw 9bh-98h system inactivity timer 0000_0000h rw abh-a8h hardware trap status 0000_0000h rw afh-ach hardware trap enable 0000_0000h rw b3h-b0h hardware trap reload enable 0000_0000h rw b7h-b4h irq reload enable 0000_0000h rw d1h-c0h gpio [17:0] 00h rw d7h-d4h gpio pin interrupt status 0000_0000h rw dbh-d8h gpio pin interrupt enable 0000_0000h rw dfh-dch gpio output clock 0 and 1 ffff_ffffh rw e1h-e0h smbus global status 0000h rw e3h-e2h smbus global control 0000h rw e5h-e4h smbus host address 0000h rw e7h-e6h smbus host data 0000h rw e8h smbus host command field 00h rw e9h smbus host block data fifo 00h rw
18 6 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information ebh-eah smbus host -as-slave data 0000h rw edh-ech smbus host-as-slave device address 0000h rw eeh smbus host-as-slave host address 10h rw efh smbus snoop address 10h rw note: the base pointer for the power management i/o-mapped registers is function 3, offset 58 (pm00). table 63. power management i/o-mapped registers (continued) offset function default access
chapter 7 registers 187 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.4 legacy i/o registers this group of i/o registers includes keyboard and mouse controllers, dma controllers, interrupt controllers, and timer/counters, as well as a number of miscellaneous ports originally implemented using discrete logic on the original pc/at. these registers are implemented in an industry- standard manner for backwards compatibility with previous generations of pc hardware. the legacy i/o registers are listed for reference only. detailed descriptions of the actions and programming of these registers are given in other industry publications. all of the registers reside in i/o space. they are grouped according to the AMD-756 peripheral bus controller functions. the i/o port address and access type are given for each register. 7.4.1 keyboard controller registers the keyboard controller handles the keyboard and mouse interfaces using port 60h and port 64h. reads from port 64h return a status byte. writes to port 64h are command codes. data is transferred via port 60h.
18 8 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information . legacy i/o registers: keyboard/mouse status port 64h bit name description reset access type 7pe parity error. when this bit is set, it indicates a parity error (even parity) on the last byte received from the keyboard/mouse 0 = no parity error 1 = parity error on last byte from keyboard/mouse 0ro 6grt general receive/transmit timeout. 0 = no error 1 = timeout error occurred. 0ro 5mob mouse output buffer full. 0 = buffer empty 1 = mouse buffer full 0ro 4ks keylock status. 0 = locked 1= free (keylock not set) 0ro 3cd command/data. 0 = data write 1 = command write 0ro 2sf system flag. 0 = power-on 1 = self test successful 0ro 1ib input buffer full. 0 = keyboard input buffer empty 1 = keyboard input buffer full 0ro 0kob keyboard output buffer full. 0 = keyboard output buffer empty 1 = keyboard output buffer full 0ro legacy i/o registers: keyboard/mouse command port 64h bit name description reset access type 7-0 keyboard/mouse command. value of the specific keyboard/mouse command (see table 64) 0wo
chapter 7 registers 189 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 64. keyboard controller command codes command code keyboard command code description 20h read control byte (next byte is control byte) 60h write control byte (next byte is control byte) 9xh write the value of x (bits 0 ? 3) to input ports p10 ? p13 a1h output keyboard controller version number a4h test if password is installed (returns f1h to indicate ? not installed ? ) a7h disable mouse interface a8h enable mouse interface a9h mouse interface test (results in port 60h) 0 = pass, 1 = clock stuck low, 2 = clock stuck high, 3 = data stuck low, 4 = data stuck high, ff = general error aah kbc self test (results in port 60h) 55h = ok, fch = not ok abh keyboard interface test (results in port 60h) 0 = ok, 1 = clock stuck low, 2 = clock stuck high, 3 = data stuck low, 4 = data stuck high, ff = general error adh disable keyboard interface aeh enable keyboard interface afh return version number b7h ? b0h set pin low (each value operates on one pin - b0h:p10, b1h:p1, b2h:p2, b3h:p3, b4h:p22, b5h:p23h, b6:p14, b7h:p15) bfh ? b8h set pin high (each value operates on one pin - b0h:p10, b1h:p1, b2h:p2, b3h:p3, b4h:p22, b5h:p23h, b6:p14, b7h:p15) c0h read input port (read ports p10 ? p17 input data to the output buffer) c1h poll input port low (read input data on input ports p13 ? p11 repeatedly and put results in bits 7 ? 5 of status register) c2h poll input port high (read input data on input ports p17 ? p15 repeatedly and put results in bits 7 ? 5 of status register) c8h unblock p22 ? p23 (use before command d1h to change the active mode) c9h reblock p22 ? p23 (protection mechanism for d1h command) cah read mode (output kbc mode info to port 60 output buffer) bit 0 = 0 for isa, bit 0 = 1 for ps/2 d0h read port (copy p27 ? p20 output values to port 60h) d1h write port (data byte following is written to keyboard output port as if it came from the keyboard) d2h write keyboard output buffer and clear status bit 5 (write following byte to keyboard) d3h write mouse output buffer and set status bit 5 (write the following byte to the mouse, and put the value in mouse input buffer so it appears to have come from the mouse) d4h write mouse (write the following byte to the mouse)
19 0 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information the kbc control register is accessible by writing commands 20h/60h to the command port (64h). the control byte is written by first sending a value of 60h to the command port, then sending the control byte value to port 60h. the control register can be read by sending a command of 20h to port 64h, waiting for an output-buffer-full status reading on bit 5 or bit 0 of 64h, then reading the control byte value from port 60h. e0h read test inputs (t0 ? t1 read to bits 0 ? 1 of respective byte, bit0 = keyboard clock, bit 1 = mouse clock) exh set input ports p23 ? p21 per command bits 3 ? 1 fxh pulse input ports p23 ? p20 low for 6 sec per command bits 3 ? 0 note: 1. codes not listed are undefined or their functions are eliminated by direct control of the keyboard controller logic. 2. the keyboard controller is compatible with industry-standard 82c42 keyboard controllers except that, because of its integrati on into a larger chip, many of the i/o port pins are not available for external use as general-purpose i/o pins, even when p13 ? p16 are set during power-up as strapping options. consequently, many of the commands in this table work but perform no useful function, such as commands that set p12 ? p17 high or low. 3. setting p10 ? 11, p22 ? 23, p26 ? 27, and t0 ? 1 high or low serve no useful purpose because these bits are used to implement the keyboard and mouse ports and are directly controlled by keyboard controller logic. table 64. keyboard controller command codes (continued) command code keyboard command code description legacy i/o registers: kbc control port 60h and 64h bit name description reset access type 7 reserved. always reads 0. 0 rw 6pcc pc compatibility. this bit controls conversion of the keyboard scan codes to pc format. 0 = disable scan conversion 1 = convert scan codes 1rw 5md mouse disable. 0 = enable mouse 1 = disable mouse 0rw 4kd keyboard disable. 0 = enable keyboard 1 = disable keyboard 0rw 3kld keyboard lock disable. 0 = keyboard lock enabled 1 = keyboard lock disabled 0rw 2sflg system flag. this bit can be read back as [status register] port 64h, bit 2. 0 rw
chapter 7 registers 191 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information traditional keyboard controllers traditional (non-integrated) keyboard controllers have an input port and an output port with specific pins dedicated to certain functions and other pins available for general purpose i/o. specific commands are provided to set these pins high and low. all outputs are open-collector to allow the pins to function as inputs. the output value for that pin is set high (non-driving), and the desired input value is read on the input port. these ports are defined as shown in table 65. 1mie mouse interrupt enable. 0 = disable mouse interrupts 1 = enable mouse interrupts (on irq12 when mouse output buffer is full) 0rw 0 kbe keyboard interrupt enable. 0 = disable keyboard interrupts 1 = enable keyboard interrupts (on irq1 when keyboard output buffer is written) 1rw legacy i/o registers: kbc control port 60h and 64h bit name description reset access type table 65. traditional port pin definition bit input port locode hicode 0p10 ? keyboard data in b0 b8 1p11 ? mouse data in b1 b9 2p12 ? turbo pin (ps/2 mode only) b2 ba 3p13 ? user defined b3 bb 4p14 ? user defined b6 be 5p15 ? user defined b7 bf 6p16 ? user defined ?? 7p17 ? undefined ?? bit output port locode hicode 0p20 ? sysrst (1 = execute reset) ?? 1p21 ? gatea20 (1 = a20 enabled) ?? 2p22 ? mouse data out b4 bc 3p23 ? mouse clock out b5 bd 4p24 ? keyboard obf interrupt (irq1) ?? 5p25 ? mouse obf interrupt (irq12) ?? 6p26 ? keyboard clock out ??
192 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.4.2 dma controller i/o registers master dma controller registers channels 0 ? 3 of the master dma controller control system dma channels 0 ? 3. there are 16 master dma controller registers, as shown in table 66. 7p27 ? keyboard data out ?? bit test port locode hicode 0t0 ? keyboard clock in ?? 1t1 ? mouse clock in ?? table 65. traditional port pin definition bit input port locode hicode legacy i/o registers: keyboard controller input buffer port 60h bit name description reset access type 7-0 input buffer. this write-only register should only be written when port 64h, bit 1 is 0. a value of 1 indicates that the input buffer is full. 0wo legacy i/o registers: keyboard controller output buffer (ro) port 60h bit name description reset access type 7-0 output buffer. this read-only register should only be read when port 64h, bit 0 is 1. a value of 0 indicates that the output buffer is empty. 0 table 66. master dma controller ports 00h ? 0fh i/o address bits 15 ? 0 register name access type 0000_0000_000x_0000 ch 0 base/current address rw 0000_0000_000x_0001 ch 0 base/current count rw 0000_0000_000x_0010 ch 1 base/current address rw 0000_0000_000x_0011 ch 1 base/current count rw 0000_0000_000x_0100 ch 2 base/current address rw 0000_0000_000x_0101 ch 2 base/current count rw 0000_0000_000x_0110 ch 3 base/current address rw 0000_0000_000x_0111 ch 3 base/current count rw 0000_0000_000x_1000 status/command rw
chapter 7 registers 193 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information slave dma controller registers channels 0 ? 3 of the slave dma controller control system dma channels 0 ? 3. there are 16 slave dma controller registers, as shown in table 67. 0000_0000_000x_1001 write request wo 0000_0000_000x_1010 write single mask wo 0000_0000_000x_1011 write mode wo 0000_0000_000x_1100 clear byte pointer f/f wo 0000_0000_000x_1101 master clear wo 0000_0000_000x_1110 clear mask wo 0000_0000_000x_1111 r/w all mask bits rw note: not all address bits are decoded. table 66. master dma controller ports 00h ? 0fh i/o address bits 15 ? 0 register name access type table 67. slave dma controller ports c0h ? dfh i/o address bits 15 ? 0 register name access type 0000_0000_1100_000x ch 0 base/current address rw 0000_0000_1100_001x ch 0 base/current count rw 0000_0000_1100_010x ch 1 base/current address rw 0000_0000_1100_011x ch 1 base/current count rw 0000_0000_1100_100x ch 2 base/current address rw 0000_0000_1100_101x ch 2 base/current count rw 0000_0000_1100_110x ch 3 base/current address rw 0000_0000_1100_111x ch 3 base/current count rw 0000_0000_1101_000x status/command rw 0000_0000_1101_001x write request wo 0000_0000_1101_010x write single mask wo 0000_0000_1101_011x write mode wo 0000_0000_1101_100x clear byte pointer f/f wo 0000_0000_1101_101x master clear wo 0000_0000_1101_110x clear mask wo 0000_0000_1101_111x r/w all mask bits rw note: not all address bits are decoded.
194 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information dma page registers there are eight dma page registers, one for each dma channel. these registers provide bits 16 ? 23 of the 24-bit address for each dma channel. bits 0 ? 15 are stored in registers in the master and slave dma controllers. the dma page registers are located at the i/o port addresses shown in table 68. 7.4.3 interrupt controller registers master interrupt controller registers the master interrupt controller controls system interrupt channels 0 ? 7. the two registers are shown in table 69. slave interrupt controller registers the slave interrupt controller controls system interrupt channels 8 ? 15. the two registers are shown in table 70. table 68. dma page ports 80h ? 8fh i/o address bits 15 ? 0 register name access type 0000_0000_1000_0111 ch 0 dma page (m ? 0) rw 0000_0000_1000_0011 ch 1 dma page (m ? 1) rw 0000_0000_1000_0001 ch 2 dma page (m ? 2) rw 0000_0000_1000_0010 ch 3 dma page (m ? 3) rw 0000_0000_1000_1111 ch 4 dma page (m ? 4) rw 0000_0000_1000_1011 ch 5 dma page (m ? 5) rw 0000_0000_1000_1001 ch 6 dma page (m ? 6) rw 0000_0000_1000_1010 ch 7 dma page (m ? 7) rw table 69. master interrupt controller ports 20h ? 21h i/o address bits 15 ? 0 register name 0000_0000_001x_xxx0 master interrupt control rw 0000_0000_001x_xxx1 master interrupt mask rw note: not all address bits are decoded. table 70. slave interrupt controller ports a0h ? a1h i/o address bits 15 ? 0 register name 0000_0000_101x_xxx0 slave interrupt control rw 0000_0000_101x_xxx1 slave interrupt mask rw note: not all address bits are decoded.
chapter 7 registers 195 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.4.4 interrupt controller shadow registers the following shadow registers are enabled by setting bit 4 of offset 47h. if the shadow registers are enabled, they are read back at the indicated i/o ports instead of the standard interrupt controller registers. writes to the standard ports are directed to the standard interrupt controller registers. interrupt controller shadow registers: master interrupt control shadow port 20h bit name description reset access type 7-5 reserved. always reads 0. 0 ro 4ocw3-5 special mask mode (ocw3, bit 5). 0 = normal masked mode 1 = special masked mode xro 3ocw2-7 priority (ocw2, bit 7). 0 = fixed 1 = rotate xro 2 icw4-4 special fully nested mode (icw4, bit 4). setting this bit turns on the special fully nested mode. 0 = off 1 = on xro 1 icw4-1 end of interrupt (icw4, bit 1). 0 = normal eoi 1 = automatic eoi xro 0 icw1-3 trigger type (icw1, bit 3). 0 = edge 1 = level xro note: 1. ocw = operational command word 2. icw = initialization command word interrupt controller shadow registers: master interrupt mask shadow port 21h bit name description 0-state 1-state 7-5 reserved. always reads 0. 0 ro 4-0 t7 ? t3 of the interrupt vector address. xro
19 6 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information interrupt controller shadow registers: slave interrupt control shadow port a0h bit name description reset access type 7-5 reserved. always reads 0. 0 ro 4ocw3-5 special mask mode (ocw3, bit 5). 0 = normal masked mode 1 = special masked mode xro 3ocw2-7 priority (ocw2, bit 7). 0 = fixed 1 = rotate xro 2 icw4-4 special fully nested mode (icw4, bit 4). setting this bit turns on the special fully nested mode. 0 = off 1 = on xro 1 icw4-1 end of interrupt (icw4, bit 1). 0 = normaleoi 1 = automatic eoi xro 0 icw1-3 trigger type (icw1, bit 3). 0 = edge 1 = level xro note: 1. ocw = operational command word 2. icw = initialization command word interrupt controller shadow registers: slave interrupt mask shadow port a1h bit name description reset access type 7-5 reserved. always reads 0. 0 ro 4-0 t7 ? t3 of the interrupt vector address. xro
chapter 7 registers 197 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.4.5 timer/counter registers there are four timer/counter registers, as shown in table 71. 7.4.6 cmos/rtc registers the system real-time clock (rtc) is part of the cmos block. the rtc control registers are located at specific offsets in the cmos data area (00h ? 0dh and 7dh ? 7fh). detailed descriptions of cmos/rtc operation and programming can be obtained from several industry publications. for reference, the definition of the rtc register locations and bits are summarized in table 72. table 71. timer/counter ports 40h ? 43h i/o address bits 15 ? 0 register name 0000 0000 010x xx00 timer/counter 0 count rw 0000 0000 010x xx01 timer/counter 1 count rw 0000 0000 010x xx10 timer/counter 2 count rw 0000 0000 010x xx11 timer/counter command mode wo note: not all address bits are decoded. table 72. cmos register summary offset description binary range bcd range 00h seconds 00h ? 3bh 00h ? 59h 01h seconds alarm 00h ? 3bh 00h ? 59h 02h minutes 00h ? 3bh 00h ? 59h 03h minutes alarm 00h ? 3bh 00h ? 59h o4h time: hours am 12 hour clock 01h ? 1ch 01h ? 12h pm 12 hour clock 81h ? 8ch 81h ? 92h 24 hour clock 00h ? 17h 00h ? 23h 05h alarm: hours am 12 hour clock 01h ? 1ch 01h ? 12h pm 12 hour clock 81h ? 8ch 81h ? 92h 24 hour clock 00h ? 17h 00h ? 23h 06h day of the week (sunday = 1: saturday = 7) 01h ? 07h 01h ? 07h 07h day of the month 01h ? 1fh 01h ? 31h
19 8 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 08h month 01h ? 0ch 01h ? 12h 09h year 00h ? 63h 00h ? 99h 0ah bit 7 update in progress bits 6 ? 4 divide (for 1hz clock generation) 001 = divide by 4096k 010 = divide by 32k 011 = divide by 1024 100 = divide by 32 101 = rtcx_in drives 1 hz direct 110 = rtc held in reset 111 = rtc held in reset bits 3 ? 0 rate select for periodic interrupt 0bh bit 7 inhibit update transfers bit 6 periodic interrupt enable bit 5 alarm interrupt enable bit 4 update ended interrupt enable bit 3 no function bit 2 data mode (0 = bcd, 1 = binary) bit 1 hours format (0 = 12, 1 = 24) bit 0 daylight saving enable 0ch bit 7 interrupt request flag bit 6 periodic interrupt flag bit 5 alarm interrupt flag bit 4 update ended flag bits 3 ? 0 unused (always reads 0) 0dh bit 7 vrt (= 1 if vbat voltage is ok) bits 6 ? 0 unused (always reads 0) 0eh ? 7ch software-defined storage registers (111 bytes) 7dh date alarm 01h ? 0fh 01h ? 31h 7eh month alarm 01h ? 0ch 01h ? 12h 7fh century field 13h ? 14h 19h ? 20h 80h ? ffh software-defined storage registers (128 bytes) table 72. cmos register summary (continued) offset description binary range bcd range
chapter 7 registers 199 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information there are three pairs of registers for accessing the on-chip cmos ram. ports 70h ? 71h and 72h ? 73h access the ram when the internal rtc is enabled, and ports 74h ? 75h access the ram when the internal rtc is disabled. ports 70h ? 71h are compatible with relevant pc industry standards and access the lower 128 bytes of the 256-byte on-chip cmos ram. ports 72h ? 73h access the full extended 256-byte space. these ports can be used only if the internal rtc is enabled by setting function 0, offset 5ah, bit 2. if this bit is cleared, accesses to ports 70h ? 71h and 72h ? 73h will be directed to an external rtc. ports 74h ? 75h access the full on-chip extended 256-byte space when the on-chip rtc is disabled. these ports can be accessed only if function 0, offset 5bh, bit 1 is set to enable the internal rtc sram and if offset 48h, bit 3 is set to enable access to port 74h ? 75h. cmos/rtc registers: cmos address port 70h bit name description reset access type 7nmid nmi disable. when enabled, nmi is asserted on encountering iochck# on the isa bus or serr# on the pci bus. 0 = enabled 1 = disabled 1wo 6-0 cmos address (128 bytes). xwo cmos/rtc registers: cmos data port 71h bit name description reset access type 7-0 cmos address (128 bytes). xrw cmos/rtc registers: cmos address port 72h bit name description reset access type 7-0 cmos address (256 bytes). xrw
200 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information cmos/rtc registers: cmos data port 73h bit name description reset access type 7-0 cmos data (256 bytes). xrw cmos/rtc registers: cmos address port 74h bit name description reset access type 7-0 cmos address (256 bytes). this port is intended to be used to access the internal cmos ram when an external real-time clock is selected. xrw cmos/rtc registers: cmos data port 75h bit name description reset access type 7 cmos data (256 bytes). this port is intended to be used to access the internal cmos ram when an external real-time clock is selected. xrw
chapter 7 registers 201 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.4.7 miscellaneous i/o functions miscellaneous i/o register 1 port 61h bit name description reset access type 7 serr serr# latch. this bit is set high when pci-bus signal serr# is asserted and remains set until cleared by bit 2 of this register. 0 = no serr# 1 = pci bus signal serr# asserted 0ro 6iocha iochck# active. this bit is set when the isa bus iochck# signal is asserted. once set, this bit may be cleared by setting bit 3 of this register. bit 3 should be cleared to enable recording of the next iochck#. iochck# generates an nmi to the cpu if nmi is enabled. 0 = no iochck# 1 = isa bus signal iochck# asserted 0ro 5t/c2o timer/counter 2 output. this bit is an unsynchronized reflection of the output of timer/counter 2. 0ro 4rd refresh detected. this bit toggles on every rising edge of the isa bus refresh# signal. 0 ro 3iochd iochck# disable. setting this bit clears bit 6 of this register and disables iochck# assertions. 0 = iochck# enabled 1 = iochck# disabled 0rw 2 clrserr clrserr setting this bit clears bit 6 of this register. when low bit 7 of this register can be set. 0 = allow bit 7 to function 1 = clears bit 7 0rw 1se speaker enable. setting this bit enables the timer/counter 2 output to drive the spkr pin. 0 = disabled 1 = enabled 0rw 0t/c2d timer/counter 2 enable. 0 = disabled 1 = enabled 0rw miscellaneous i/o register 2 port 92h bit name description reset access type 7-2 reserved. always reads 0. 0 1a20ale a20 address line enable. writing 0 to this bit forces the a20 line to 0 disabling a20. 0 = disabled 1 = enabled 0rw 0hsr high speed reset. setting this bit pulses reset to switch from protected mode to real mode. 0 = disabled 1 = pulse reset 0rw
202 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.5 function 0 registers (pci-isa bridge) function 0 registers (pci-isa bridge): pci configuration space header offset 01h ? 00h bit name description reset access type 15-0 vendor id. always reads 1022h. 1022h ro function 0 registers (pci-isa bridge): device id (ro) offset 03h ? 02h bit name description reset access type 15-0 device id. always reads 7408h. 7408h ro function 0 registers (pci-isa bridge): command offset 05h ? 04h bit name default description access type 15-4 0 reserved. always reads 0. 3sce1 special cycle monitoring. 0 = ignores pci shut down special cycles. 1 = responds to pci shutdown cycles by generating a pulse over either cpurst# or init#. . rw 2bm1 bus master. always reads 1. 1 = enables pci-isa bridge to be a master on the pci bus. ro 1ms1 memory space. always reads 1. 1 = enable access to the isa bus memory space. ro 0ios1 i/o space. always reads 1. 1 = enable access to the isa i/o space including the isa bus and all the isa registers mapped in AMD-756. ro function 0 registers (pci-isa bridge): status offset 07h ? 06h bit name default description access type 15 dpe 0 detected parity error. always reads 0. 0 = no error 1 = error ro 14 sse 0 signaled system error. always reads 0. 0 = no error 1 = error ro 13 sma 0 signaled master abort. 0 = no abort 1 = AMD-756 controller generates master abort. rwc 12 rta 0 received target abort. 0 = no abort 1 = AMD-756 controller receives target abort. rwc 11 sta 0 signaled target abort. always reads 0. 0 = no abort 1 = AMD-756 controller receives target abort. ro 10-9 dt 01 devsel# timing. fixed at 01 = medium timing. ro 8dpd0 data parity detected. always reads 0. ro 7fbtb0 fast back-to-back enable. always reads 0. ro 6udf0 user-definable features. always reads 0. ro 5c660 66-mhz capable. always reads 0. ro
chapter 7 registers 203 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4-0 reserved. always reads 0. function 0 registers (pci-isa bridge): revision id offset 08h bit name default description access type 7-0 01h revision id. 01h = revision a. ro function 0 registers (pci-isa bridge): programming interface offset 09h bit name default description access type 7-0 00h programming interface. always reads 00h. ro function 0 registers (pci-isa bridge): sub-class code offset 0ah bit name default description access type 7-0 01h sub-class code. always reads 01h. ro function 0 registers (pci-isa bridge): base class code offset 0bh bit name default description access type 7-0 06h base class code. always reads 06h. ro function 0 registers (pci-isa bridge): cache offset 0ch bit name default description access type 7-0 00h cache. always reads 00h. ro function 0 registers (pci-isa bridge): latency offset 0dh bit name default description access type 7-0 00h latency. always reads 00h. ro function 0 registers (pci-isa bridge): header type offset 0eh bit name default description access type 7-0 80h header type. always reads 80h. ro function 0 registers (pci-isa bridge): status offset 07h ? 06h bit name default description access type
204 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.5.1 isa bus control function 0 registers (pci-isa bridge): bist offset 0fh bit name default description access type 7-0 00h bist. always reads 0. ro function 0 registers (pci-isa bridge): subsystem id and subsystem vendor id offset 2fh ? 2ch bit name default description access type 31-16 0000h subsystem id. can be configured via offset 50h. ro 15-0 0000h subsystem vendor id. can be configured via offset 50h. ro function 0 registers (pci-isa bridge): isa bus control 1 offset 40h bit name default description access type 7-4 0 reserved. 3iort0 i/o recovery time. 0 = there is a minimum of 5.5 bclk cycles between the trailing edge of an isa i/o command signal (ior# or iow#) and the leading edge of the next isa i/o command signal. 1 = there is a minimum of 13.5 bclk cycles between adjacent i/o cycles. this bit does not affect isa bus memory cycles. rw 20 reserved . 1rws0 rom wait states. 0 = the isa command signal (memr# or memw#) is 2.0 bclk cycles (wait states) in duration. 1 = the isa command signal is 1.0 bclk cycles (wait state) in duration. rw 0romw0 rom write. 0 = the romcs# is disabled and does not become active during writes to bios address space. memw# is active during writes to address space near 1 megabyte but not near 4 gigabytes. 1 = the romcs# and memw# pins are enabled and become active during writes to the bios address space. rw function 0 registers (pci-isa bridge): isa bus control 2 offset 41h bit name default description access type 7mlen0 mouse lock enable. 0= this function is disabled. 1 = this function is enabled. 60 reserved. always reads 0. 5 p92fr 0 port 92 fast reset. 0 = disables writes to port92[0]. 1 = enables writes to port92[0]. rw 40 reserved. always reads 0.
chapter 7 registers 205 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 3ddmac0 double dma clock. 0 = dma clock is bclk (isa clock) divided by two. 1 = dma clock is the same frequency as bclk. this bit does not affect type f dma mode. rw 2 ? 10 reserved. always reads 0 0rtm0 isa refresh cycle. 0 = isa bus refresh cycles are disabled. 1 = isa bus refresh cycles are enabled and occur at a frequency determined by timer 1 of the pit. rw function 0 registers (pci-isa bridge): rom decode control offset 43h bit name default description access type 7 rd7 0 fffe_0000h ? fffe_ffffh 0 = exclude 1 = include rw 6 rd6 0 fff8_0000h ? fffd_ffffh 0 = exclude 1 = include rw 5 rd5 0 000e_8000h ? 000e_ffffh 0 = exclude 1 = include rw 4 rd4 0 000e_0000h ? 000e_7fffh 0 = exclude 1 = include rw 3 rd3 0 000d_8000h ? 000d_ffffh 0 = exclude 1 = include rw 2 rd2 0 000d_0000h ? 000d_7fffh 0 = exclude 1 = include rw 1 rd1 0 000c_8000h ? 000c_ffffh 0 = exclude 1 = include rw 0 rd0 0 000c_0000h ? 000c_7fffh 0 = exclude 1 = include rw note: setting each bit includes the associated address range in the romcs# decode. the romcs# pin is shared with the external keyboar d chip select function and is used to enable accesses to the system bios. romcs# always decodes accesses to 000f_0000h ? 000f_ffffh and ffff_0000h ? ffff_ffffh and can also be enabled to decode the address ranges specified by this register. function 0 registers (pci-isa bridge): type f dma control offset 45h bit name default description access type 7 6ch70 dma type f on channel 7. 0 = disabled 1 = enable type f dma cycles . rw 5ch60 dma type f on channel 6. 0 = disabled 1 = enable type f dma cycles . rw 4ch50 dma type f on channel 5. 0 = disabled 1 = enable type f dma cycles . rw 3ch30 dma type f on channel 3. 0 = disabled 1 = enable type f dma cycles . rw 2ch20 dma type f on channel 2. 0 = disabled 1 = enable type f dma cycles . rw 1ch10 dma type f on channel 1. 0 = disabled 1 = enable type f dma cycles . rw 0ch00 dma type f on channel 0. 0 = disabled 1 = enable type f dma cycles . rw note: setting each enables type f dma cycles on the corresponding dma channel, when low at-compatible cycles are enabled. function 0 registers (pci-isa bridge): isa bus control 2 offset 41h bit name default description access type
206 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information function 0 registers (pci-isa bridge): miscellaneous control 1 offset 46h bit name default description access type 7-1 reserved. 0pmwe0 post memory write enable. 0 = (disabled) the pci targets state machine waits until the cycle is complete before passing ready back to the pci bus. 1 = (enabled) the one-dword write buffer from pci target writes to the isa bus is enabled. this buffer is only used for memory writes. rw function 0 registers (pci-isa bridge): miscellaneous control 2 offset 47h bit name default description access type 7rs 0 cpu reset source. 0 = the cpurst pin is used for processor resets. 1 = the init pin is used for processor resets. the reset generated by function 0, offset 47[pcirst] clears this bit before a cpurst or init pulse is generated. this causes reset always to use the cpurst pin. rw 6dte0 pci delay transaction enable. 0 = (disabled) pci accesses that target the isa bus are terminated with the disconnect command after the isa bus cycle is complete. this often results in a pci cycle that consumes more than the maximum 16-pclk limit and violates the pci specification revision 2.1. 1 = (enabled) pci accesses that target the isa bus and internal isa registers utilize the delayed-transaction protocol described in section 3.3.3.3 of the pci specification revision 2.1. the table below indicates how the AMD-756 peripheral bus controller behaves based on the type of cycle. rw cycle type behavior of the AMD-756 peripheral bus controller memory write write is posted. within a few pclk cycles, the bus controller terminates the write with the pci-defined disconnect command (including the transfer of data) and completes the pci cycle. the isa-bus cycle continues and subsequently completes. memory read, i/o read, and i/o write the bus controller immediately terminates the cycle with the pci-defined retry command while executing the specified isa-bus cycle. the master is obliged to keep retrying the cycle, which is terminated with retry each time by the bus controller. after the isa cycle is compete, the next master- initiated retry is terminated with the disconnect command. this transfers the data (in the case of a read) and completes the pci cycle. memory write followed by a read or i/o cycle if a memory write is posted and is immediately followed by a memory read, i/o read, or i/o write, retry commands are issued to the master, sometimes for twice as long. the posted write completes first followed by the read or i/o cycle.
chapter 7 registers 207 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5pe 0 eisa 4d0/4d1 port enable. 0 = disables the bit controls found in ei4d0 and ei4d1. 1 = enables the bit controls found in ei4d0 and ei4d1. ei4d0 and ei4d1 can be used to specify level-triggered interrupts for individual isa irq lines. pe does not affect the ability to read or write to ei4d0 and ei4d1 ? only whether the outputs of these registers control the irq lines. rw 4icsre0 interrupt controller shadow register enable. obsolete bit, should always be left in its default state. rw 3 ? 1 reserved. 0pcirst0 software pci reset. 0 = no reset 1 = causes a a 32-pclk-cycle reset pulse that resets the AMD-756 peripheral bus controller and the rest of the platform (pci bus, isa bus, and cpu) by asserting the pcirst#, rstdrv, and cpurst pins. wo function 0 registers (pci-isa bridge): miscellaneous control 3 offset 48h bit name default description access type 7 selirq8 0 select irq8. 1= the rtcirq# is selected on the ignne# pin. 0= the ignne# function is provided on the ignne# pin. rw 6-4 0 reserved. always reads 0. 3rtc74d0 extra rtc port 74/75 enable. 0 = accesses to i/o ports 74h and 75h generate normal isa bus cycles. 1 = (and if the external real time clock is selected by function 3, offset 48, bit [intrtc],) the internal real time clock sram can be accessed via i/o ports 74h for the index or address select and 75h for the data. this bit has no effect if the internal real time clock is enabled. rw 2iusbcd0 integrated usb controller enable. 0 = the usb controller is enabled. 1 = the usb controller is disabled. all usb configuration, memory, and i/o registers are inaccessible, and pci mastering ability is removed. rw 1iden0 ide controller enable. 0 = the ide controller is enabled. 1 = the ide controller is disabled. all ide configuration and i/o registers are inaccessible, and pci mastering ability is removed. rw 0tmp 1 top of pci memory decode. refer to function 0, offset 4eh for more information 0 = enabled 1 = disabled rw function 0 registers (pci-isa bridge): miscellaneous control 2 (continued) offset 47h bit name default description access type
208 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information function 0 registers (pci-isa bridge): miscellaneous control 4 offset 49h bit name default description access type 7 reserved. 6 rvlint 0 reveal hidden interrupt sources. 0 = picd[1]#, picd[0]#, wsc#, and picclk all operate as the system interrupt message bus. 1= picd[1]# is pitirq, picd[0]# is kbcirq, wsc# is sciirq, and picclk is usbirq. rw 5-4 reserved. 3isa12ma1 select 12-ma isa bus signals. 0 = isa bus signals can source and sink 24 ma. 1 = isa bus signals can source and sink 12 ma. rw 2cmlkb80 cmos ram b8h ? bfh locked. 0 = these cmos locations are rw. 1 = writes to these cmos locations are ignored, and reads always return ffh. note: once this bit is set, it can only be cleared by a pwrgd reset. see note 1cmlk380 cmos ram 38h ? 3fh locked. 0 = these cmos locations are rw. 1 = writes to these cmos locations are ignored, and reads always return ffh. note: once this bit is set, it can only be cleared by a pwrgd reset. see note 0prisch0 pci master access priority. 0 = the access priority is isa bus, usb controller, ide controller. 1 = the access priority is isa bus, ide controller, usb controller. rw function 0 registers (pci-isa bridge): ide interrupt routing offset 4ah bit name default description access type 7 pgnt1st 1 wait for pgnt before grant to isa master/dma. 0 = (disabled) no waiting occurs. 1 = (enabled) wait until the pci bus is granted to the AMD-756 peripheral bus controller before dma acknowledge is passed back to the isa bus for the dma or master data transfer. rw 6-4 000 reserved. 3-2 sideirq 01 secondary ide irq routing. these bits determine the irq for the secondary ide controller. default is irq15. 00 = i rq14 10=i rq10 01 = irq15 11=irq11 rw 1-0 pideirq 00 primary ide irq routing. these bits determine the irq for the primary ide controller. default is irq14. 00 = i rq14 10=i rq10 01 = irq15 11=irq11 rw
chapter 7 registers 209 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information note: when function 1 offset 08 bit 8 is high, then irq14 is assumed to be the ide primary port interrupt pin, so pideirq should be s et to its default value. when function 1 offset 08 bit 10 is high, then irq15 is assumed to be the ide secondary port interrupt pin, so pideirq should b e set to its default value. function 0 registers (pci-isa bridge): ide interrupt routing offset 4ah bit name default description access type
210 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information function 0 registers (pci-isa bridge): isa dma/master memory access control 1 offset 4ch function 0 registers (pci-isa bridge): ioapic offset 4bh bit name default description access type 7-5 reserved. 4-3 apiccs[1:0] 00 apic clock select. selects the source and frequency of the picclk as shown in table 73 rw 2sci2ioa00 sci to ioapic redirection register 22. 1 = the sci output of power management is routed through irq22 of the ioapic. function 3 offset 42 [scisel] is disabled. 0 = irq22 of the ioapic is driven with the output of the gpio16 input path. function 3 offset 42 [scisel] operates normally. rw 1 smi2ioa 0 smi to ioapic redirection register 23. 1 = the smi output of power management is routed through irq23 of the ioapic and the smi# pin does not become active. 0 = irq23 of the ioapic is driven with the output of the gpio17 input path and the smi# pin is controlled with the internal smi logic. rw 0apicen0 ioapic enable. 0 = accesses to the ioapic register space are ignored and the imb is not used. 1 = the ioapic is enabled and the imb is used to transmit all interrupts. rw table 73. picclk frequency and source apiccs[1:0] frequency source 00b pclk divided by 4 (8.3 mhz. max) AMD-756 drives the picclk 01b pclk divided by 2 (16.7 mhz max) AMD-756 drives the picclk 10b pclk (33.3 mhz max) AMD-756 drives the picclk 11b unknown. in this mode, a clock source of 33 mhz or less is required. picclk is driven by an external component. bit name default description access type 7-0 pmhba 0 pci memory hole bottom address. these bits correspond to ha[23:16]. rw note: access to the memory defined in the pci memory hole is not forwarded to pci. this function is disabled if the top address is le ss than or equal to the bottom address.
chapter 7 registers 211 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information function 0 registers (pci-isa bridge): isa dma/master memory access control 2 offset 4dh bit name default description access type 7-0 pmhta 0 pci memory hole top address. these bits correspond to ha[23:16] rw note: 1. access to the memory defined in the pci memory hole is not forwarded to pci. this function is disabled if the top address is less than or equal to the bottom address. 2. isa master and dma access to the memory define by offset 4ch(above) and offset 4dh (below) will not cause pci cycles. function 0 registers (pci-isa bridge): isa dma/master memory access control 3 offset 4fh ? 4eh bit name default description access type 15-12 0000 top of pci memory for isa dma/master accesses*. determines the highest memory address available for isa dma/master memory accesses. 0000 =1 mbyte 0001 =2 mbytes . . 1111 =16 mbytes rw 11 0 forward e0000h ? effffh. 0 = do not forward. 1 = forward rw 10 0 forward a0000h ? bffffh. 0 = do not forward. 1 = forward . rw 91 forward 80000h ? 9ffffh. 0 = do not forward. 1 = forward . rw 81 forward 00000h ? 7ffffh. 0 = do not forward. 1 = forward . rw 70 forward dc000h ? dffffh. 0 = do not forward. 1 = forward . rw 60 forward d8000h ? dbfffh. 0 = do not forward. 1 = forward . rw 50 forward d4000h ? d7fffh. 0 = do not forward. 1 = forward . rw 40 forward d0000h ? d3fffh. 0 = do not forward. 1 = forward . rw 30 forward cc000h ? cffffh. 0 = do not forward. 1 = forward . rw 20 forward c8000h ? cbfffh. 0 = do not forward. 1 = forward . rw 10 forward c4000h ? c7fffh. 0 = do not forward. 1 = forward . rw 00 forward c0000h ? c3fffh. 0 = do not forward. 1 = forward . rw note: isa dma/masters that access addresses higher than the top of pci are not directed to the pci bus. function 0 registers (pci-isa bridge): subsystem id and subsystem vendor id offset 53h ? 50h bit name default description access type 31-16 0 subsystem id. rw 15-0 0 subsystem vendor id. rw
212 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.5.2 distributed dma control 7.6 function 1 registers (enhanced ide controller) eide controller registers for the ide controller are located in function 1 of the AMD-756 peripheral bus controller pci configuration space and are accessed through pci configuration mechanism #1 via address 0cf8h/0cfch. the AMD-756 peripheral bus controller enhanced ide controller interface is fully compatible with the sff 8038i v.1.0 specification. there are two sets of software-accessible registers, the pci configuration registers and the bus master ide i/o registers. function 0 registers (pci-isa bridge): distributed dma ch n base/enable see table 74. bit name default description access type 15-4 ddbadd 0 channel n base address bits. this field specifies address bits [15:4] of the 16-byte block of i/o mapped registers in the dma slave. accesses to legacy dma registers are redirected to registers in this block if ce is enabled. rw 3ce 0 channel n enable. 0 = disabled 1 = enabled rw 2-0 0 reserved. always reads 0. table 74. dma channel offset mapping offset distributed dma channel 61h ? 60h channel 0 63h ? 62h channel 1 65h ? 64h channel 2 67h ? 66h channel 3 6bh ? 6ah channel 5 6dh ? 6ch channel 6 6fh ? 6eh channel 7
chapter 7 registers 213 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.6.1 function 1 pci configuration space header function 1 registers (eide controller): vendor id offset 01h ? 00h bit name default description access type 15-0 00010000 00100010b vendor id. this is a read-only register containing the value 1022h. ro function 1 registers (eide controller): device id offset 03h ? 02h bit name default description access type 15-0 01110100 00001001b device id. this is a read-only register containing the value 7409 h. ro function 1 registers (eide controller): command offset 05h ? 04h, bit name default description access type 15-3 0 reserved. always reads the default values. 2bm 0 bus master enable. scatter -gather operation can be issued only when this bit is enabled. 0 = disabled 1 = enabled rw 1ms 0 memory space. this bit is fixed in the low state. 0 = access to memory mapped space of the ide controller is disabled. ro 0ios 0 i/o space. 0 = (disabled) the device does not respond to any i/o addresses for either compatible or native mode. 1 = (enabled) the device responds to i/o addresses for either compatible or native modes. rw
214 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information function 1 registers (eide controller): status offset 07h ? 06h bit name default description access type 15 dpe 0 detected parity error. this bit is fixed at 0. ro 14 sse 0 signalled system error. always reads 0. ro 13 rma 0 signalled ide master abort. this bit is set by the hardware when bus master ide cycle is terminated with a master abort. rwc 12 rta 0 received target abort. this bit set high by the hardware when a target abort command is received from the pci bus during a master ide initiated master cycle. rwc 11 sta 0 signalled target abort. always reads 0. ro 10-9 dt 01 devsel# timing. these bits are fixed at 01b, which is medium timing. ro 8-0 0 reserved. always reads 0. function 1 registers (eide controller): revision id offset 08h bit name default description access type 7-0 0000010b revision id. this is a read-only register containing the revision code for the ide controller, 02h = revision c. ro function 1 registers (eide controller): programming interface offset 09h bit name default description access type 7midec1 master ide capability. always reads 1. ro 6-4 000 reserved. always reads 0. 3spi 1 secondary programmable indicator. always reads 1. supports both modes. mode is selected by writing bit 2. ro 2scom0 secondary channel operating mode. 0 = compatibility mode function 1, offset 18 and function 1, offset 1c are ignored and not visible. address decode is based on 170h-177h, 376h. function 1, offset 3c, bits[7:0] are read-only and fixed at 00h. function 1, offset 3c, bits [15:8] are read-only and fixed at 00h. irq15 can be used by the ide controller. 1= native pci mode. function 1, offset 18 and function 1, offset 1c are visible and available for address decode. function 1, offset 3c, bits[7:0] are read-write. function 1, offset 3c, bits [15:8] are read-only and fixed at 01h. irq15 becomes nmsirq used exclusively by the secondary ide port. rw 1 ppi 1 primary programmable indicator. always reads 1. supports both modes. mode is selected by writing bit 0. ro 0pcom0 primary channel operating mode. 0 = compatibility mode function 1, offset 10 and function 1, offset 14 are ignored and not visible. address decode is based on 1f0h-1f7h, 3f6h. function 1, offset 3c, bits[7:0] are read-only and fixed at 00h. function 1, offset 3c, bits [15:8] are read-only and fixed at 00h. irq14 can be used by the ide controller. 1= native pci mode. function 1, offset 10 and function 1, offset 14 are visible and available for address decode. function 1, offset 3c, bits[7:0] are read-write. function 1, offset 3c, bits [15:8] are read-only and fixed at 01h. irq14 becomes nmpirq, used exclusively by the primary ide port. rw
chapter 7 registers 215 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 75. compatibility mode vs. native pci mode mode ide channel command block registers control block registers irq compatibility mode primary fixed at i/o offset 1f7h ? 1f0h fixed at i/o offset 3f6h 14 secondary fixed at i/o offset 177h ? 170h fixed at i/o offset 376h 15 native pci mode primary determined by offset 10h determined by offset 14h nmpi rq secondary determined by offset 18h determined by offset 1ch nmsi rq note: command register blocks are 8 bytes of i/o space, while control registers are 4 bytes of i/o space (only byte 2 is used). function 1 registers (eide controller): sub class code offset 0ah bit name default description access type 7-0 0000 0001b sub class code. contains the value 01h, indicating an ide device. ro function 1 registers (eide controller): base class code offset 0bh bit name default description access type 7-0 0000 0001b base class code. contains the value 01h, indicating a mass storage device. ro function 1 registers (eide controller): offset 0ch bit name default description 0-state 7-0 0000 0000b reserved. always reads 0. function 1 registers (eide controller): latency timer offset 0dh bit name default description access type 7 ? 0 0000 0000b latency timer. this register defines the minimum amount of time, in pci clock cycles, that the bus master can retain ownership of the bus. rw function 1 registers (eide controller): header type offset 0eh bit name default description access type 7-0 0000 0000b header type. this register contains the value 00h. ro
216 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information function 1 registers (eide controller): bist offset 0fh bit name default description access type 7-0 0000 0000b bist. this register contains the value 00h. ro function 1 registers (eide controller): primary data/command base address offset 13h ? 10h bit name default description access type 31-3 0000 0000 0000 0000 0000 0001 1111 0b primary data/command port address. these bits specify an 8-byte i/o address space that maps to the ata-compliant register set for the primary port. rw 2-0 001b value fixed at 001b. ro note: when function 1, offset 8, bit 8 is low, the primary port is in compatibility mode and this register is ignored and not visible . function 1 registers (eide controller): primary control/status base address offset 17h ? 14h bit name default description access type 31-2 0000 0000 0000 0000 0000 0011 1111 01b primary control/status port address. these bits specify an 4-byte i/o address space. only the third byte is active. for example, 3f6h is the active byte for the default base address of 3f4h. rw 1-0 01b value fixed at 01b. ro note: when function 1, offset 8, bit 8 is low, the primary port is in compatibility mode and this register is ignored and not visible .
chapter 7 registers 217 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information function 1 registers (eide controller): secondary data/command base address offset 1bh ? 18h bit name default description access type 31-3 0000 0000 0000 0000 0000 0001 0111 0b secondary data/command port address. these bits specify an 8-byte i/o address space for the command block of the device connected to the secondary ide port. rw 2 ? 0001b value fixed at 001b. ro note: when function 1, offset 8, bit 10 is low, the secondary port is in compatibility mode and this register is ignored and not visi ble. function 1 registers (eide controller): secondary control/status base address offset 1fh ? 1ch bit name default description access type 31-2 0000 0000 0000 0000 0000 0011 0111 01b secondary control/status port address. these bits specify an 4-byte i/o address space. only the third byte is active. for example, 376h is the active byte for the default base address of 374h. rw 1-0 01b value fixed at 01b. ro note: when function 1, offset 8, bit10 is low, the secondary port is in compatibility mode and this register is ignored and not visib le. function 1 registers (eide controller): bus master control registers base address (rw) offset 23h ? 20h bit name default description access type 31-4 0000 0000 0000 0000 1100 1100 0000b bus master control registers base address. these bits specify a 16-byte i/o address space compliant with the sff8038i rev. 1.0 specification. 3-0 0001b value fixed at 0001b.
218 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.6.2 ide configuration registers function 1 registers (eide controller): interrupt line offset 3ch bit name default description access type 7-0 0000 0000b interrupt line. if function 1, offset 8, bit 8 or bit 10 is set, this is a read-write register. if function 1, offset 8, bit 8 and bit 10 are cleared, then this is a read only register and reads 00h.this field is used by the os for interrupt routing information. rw or ro function 1 registers (eide controller): interrupt pin offset 3dh bit name default description access type 7-0 0000 0000b interrupt pin. these bits read 01h when function 1, offset 8, bit 8 or bit 10 is set. these bits read 00h when function 1,offset 8, bit 8 and bit 10 are both cleared. ro function 1 registers (eide controller): minimum grant offset 3eh bit name default description access type 7-0 0000 0000b minimum grant. this is a read-only register containing the value 00h. ro function 1 registers (eide controller): maximum latency offset 3fh bit name default description access type 7-0 0000 0000b maximum latency. this is a read-only register containing the value 00h. ro function 1 registers (eide controller): channel enable offset 40h bit name default description access type 7-2 0000 10b reserved. always reads 02h 1pce0 primary channel enable. 0 = disabled 1 = the primary port of the ide controller is enabled when this bit is high. rw 0sce0 secondary channel enable. 0 = disabled 1 = the primary port of the ide controller is enabled when this bit is high. rw function 1 registers (eide controller): ide configuration offset 41h bit name default description access type 7prpb0 primary ide read prefetch buffer. 0 = disabled 1 = enabled rw 6ppwb0 primary ide post write buffer. 0 = disabled 1 = enabled. only 32 bit writes to the data port are allowed when this bit is high . rw 5srpb0 secondary ide read prefetch buffer. 0 = disabled 1 = enabled rw 4spwb0 secondary ide post write buffer. 0 = disabled 1 = enabled. only 32 bit writes to the data port are allowed when this bit is high . rw 3-0 0000b reserved. these bits must remain at their default value. rw
chapter 7 registers 219 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information function 1 registers (eide controller): drive timing control offset 4bh ? 48h bit name default description access type 31-28 pd0apw 1010 primary drive 0 active pulse width. rw 27-24 pd0rt 1000 primary drive 0 recovery time. rw 2320 pd1apw 1010 primary drive 1 active pulse width. rw 19-16 pd1rt 1000 primary drive 1 recovery time. rw 15-12 sd0apw 1010 secondary drive 0 active pulse width. rw 11-8 sd0rt 1000 secondary drive 0 recovery time. rw 7-4 sd1apw 1010 secondary drive 1 active pulse width. rw 3-0 sd1rt 1000 secondary drive 1 recovery time. rw note: each field of this register defines the active pulse width and recovery time for a particular ide dior# or diow# signal. the ac tual value for each field is the encoded value plus one and indicates the number of pci clocks. the default state (a8h) results in a recovery time of 270 ns and an active pulse of 330 ns for a 30-ns pci clock. this corresponds to ata pio mode 0. function 1 registers (eide controller): address setup time offset 4ch bit name default description access type 7-6 pd0ast 11 primary drive 0 address setup time. rw 5-4 pd1ast 11 primary drive 1 address setup time. rw 3-2 sd0ast 11 secondary drive 0 address setup time. rw 1-0 sd1ast 11 secondary drive 1 address setup time. rw note: the coding for the startup timings is as follows: 00 = 1 pclk 10 = 3 pclk 01 = 2 pclk 11 = 4 pclk function 1 registers (eide controller): secondary non-1f0 port access timing offset 4eh bit name default description access type 7-4 sapw 1111 dior#/diow# active pulse width. rw 3-0 srt 1111 dior#/diow# recovery time. rw note: the actual value in the field is the encoded value plus one and indicates the number of pci clocks. function 1 registers (eide controller): primary non-1f0 port access timing offset 4fh bit name default description access type 7-4 papw 1111 dior#/diow# active pulse width. rw 3-0 prt 1111 dior#/diow# recovery time. rw note: the actual value in the field is the encoded value plus one and indicates the number of pci clocks.
220 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 76. udma extended timing ide registers comply with the sff 8038i v. 1.0 standard. the base address of these registers is determined by configuration ultra dma-33 extended timing control function 1 offset 53h-50h bit name default description access type bit name default description 0-state 31 p0mem[7] 0 primary drive 0 udma mode enable method[7]. if this bit is set, udma mode is enabled by setting the udma mode enable bit in this register. if this bit is cleared, udma mode is enabled by detecting the set feature ata command. 30 p0en[6] 0 primary drive 0 udma mode enable [6]. if this bit is set, udma mode is enabled. 29-27 0 primary drive 0 udma [5:3]. these bits are fixed at their default values. 26-24 p0ct[2:0] 0 primary drive 0 udma cycle time [2:0]. these bits are defined in table 76. 23 p1mem[7] 0 primary drive 1 udma mode enable method. if this bit is set, udma mode is enabled by setting the udma mode enable bit in this register. if this bit is cleared, udma mode is enabled by detecting the set feature ata command. 22 p1en[6] 0 primary drive 1 udma mode enable [6]. if this bit is set, udma mode is enabled. 21-19 0 primary drive 1 udma [5:3]. these bits are fixed at their default values. 18-16 p1ct[2:0] 0 primary drive 1 udma cycle time [2:0]. these bits are defined in table 76. 15 s0mem[7] 0 secondary drive 0 udma mode enable method [7]. if this bit is set, udma mode is enabled by setting the udma mode enable bit in this register. if this bit is cleared, udma mode is enabled by detecting the set feature ata command. 14 s0en[6] 0 secondary drive 0 udma mode enable [6]. if this bit is set, udma mode is enabled. 13-11 0 secondary drive 0 udma [5:3]. these bits are fixed at their default values. 10-8 s0ct[2:0] 0 secondary drive 0 udma cycle time [2:0]. these bits are defined in table 76. 7s1mem[7]0 secondary drive 1 udma mode enable method [7]. if this bit is set, udma mode is enabled by setting the udma mode enable bit in this register. if this bit is cleared, udma mode is enabled by detecting the set feature ata command. 6s1en[6]0 secondary drive 1 udma mode enable[6]. if this bit is set, udma mode is enabled. 5-3 0 secondary drive 1 udma [5:3]. these bits are fixed at their default values. 2-0 s1ct[2:0] 0 secondary drive 1 udma cycle time[2:0]. these bits are defined in table 76. note: each byte of these registers defines ultra dma-33 operation for the indicated drive. the bit definitions are consistent within each byte. cycle time [2:0] ultra dma mode cycle time 000b udma mode 2 60 ns 001b udma mode 1 90 ns 010b udma mode 0 120 ns 011b slow udma mode 0 120 ns 100b udma mode 3 45 ns 101b udma mode 4 30 ns
chapter 7 registers 221 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information register function 1, offset 20h ? 23h (see page 217). the command block primary channel is 1f0h ? 1f7h, while the secondary channel is 170h ? 177h. refer to the specification for further details. i/o register primary command offset 00h bit name default description access type 7-4 0000 reserved . always reads 0. 3rwc 0 read or write control. this bit sets the direction of the bus master transfer. this bit must not be changed when the start bit 0 is set. 0 = bus master reads. 1 = bus master writes. rw 2-1 00 reserved . always reads 0. 0 ssbm 0 start/stop bus master . write only. reads always return 0 0 = master operation is stopped. master operation cannot be stopped and resumed. if this bit is cleared while a transfer is in progress the transfer is aborted. this bit should be cleared when the data transfer is completed. 1 = bus master operation is enabled. the controller then transfers data between the ide device and memory. w i/o register primary channel status offset 02h bit name default description access type 7smplxo 0 simplex only . 0 = the primary and secondary channels can be operated at the same time. 1 = the primary and secondary channels cannot be operated at the same time. ro 6dma1 0 drive 1 dma capable. 0 = no dma capability 1 = dma capable, set by device-dependent code (bios or device driver) to indicate that drive 1 is capable of dma transfers, and has been initialized . rw 5dma2 0 drive 0 dma capable. 0 = no dma capability 1 = dma capable, set by device-dependent code (bios or device driver) to indicate that drive 0 is capable of dma transfers, and has been initialized . rw 4-3 00 reserved . always reads 0. 2 interrupt 0 interrupt. this bit is set by the rising edge of the ide interrupt line. then all data transferred from the drive is in system memory. rwc 1err 0 error. 0 = no error 1 = error rwc 0bmidea 0 bus master ide active. 0 = bus master ide is stopped. 1 = bus master ide is active. this bit is set when the start bit is set in the command register. this bit is cleared when the last transfer is done. it is also cleared when the start bit in the command register is cleared. ro
222 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information i/o table 77. primary channel status register status bit meanings bit 2 bit 0 description 00 this combination signals an error. if the error bit 1 is not set, the prd is to small. if the error bit 1 is set then there was a data transfer problem. 0 1 dma transfer in progress 10 normal completion. physical memory equal to ide transfer size 11 normal completion. physical memory greater than ide transfer size i/o register primary channel prd table address offset 07h ? 04h bit name default description access type 31-2 0 primary channel prd table address. the primary channel physical region descriptor (prd) table address is an i/o register. the descriptor table must be doubleword aligned and must not cross a 64k byte boundary in memory. rw 1-0 00 reserved. always reads 0. i/o register secondary channel command offset 08h bit name default description access type 7-4 0000 reserved. always reads 0. 3rwc 0 read or write control. this bit sets the direction of the bus master transfer. this bit must not be changed when the start bit 0 is set. 0 = bus master read. 1 = bus master write. rw 2-1 0 reserved. always reads 0. 0 ssbm 0 start/stop bus master. reads always return 0. 0 = bus master operation stopped. master operation cannot be stopped and resumed. if this bit is cleared while a transfer is in progress the transfer is aborted. this bit should be cleared when the data transfer is completed. 1 = bus master operation enabled. the controller then transfers data between the ide device and memory. i/o register secondary channel status offset 0ah bit name default description access type 7smplxo 0 simplex only. this bit indicates whether the primary and secondary channels can be operated at the same time. 0 = channels operate at the same time. 1 = channels do not operate at the same time. ro
chapter 7 registers 223 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.7 function 3 registers (power management) this section describes the acpi (advanced configuration and power interface) power management system of the AMD-756 peripheral bus controller. this system supports both acpi and legacy power management functions and is compatible with the apm v. 1.2 and acpi v. 0.9 specifications. 6dma1 0 drive 1 dma capable. 0 = no dma capability for drive 1. 1 = drive 1 is capable of dma transfers, and has been initialized. this bit is set by device- dependent code (bios or device driver) . rw 5dma2 0 drive 0 dma capable. 0 = no dma capability for drive 0. 1 = drive 0 is capable of dma transfers, and has been initialized. this bit is set by device- dependent code (bios or device driver) . rw 4-3 0 reserved . always reads 0. 2 interrupt 0 interrupt. this bit is set by the rising edge of the ide interrupt line. 0 = no interrupt 1 = all data transferred from the drive is in system memory. rwc 1err 0 error. 0 = no error 1 = error detected. rwc 0bmidea 0 bus master ide active. 0 = bus master stopped, indicates the last transfer is done, or the start bit in the command register is cleared. 1 = bus master active, indicates the start bit is set in the command register. ro i/o register secondary channel prd table address offset 0fh ? 0ch bit name default description access type 31-0 0 secondary channel prd table address. the secondary channel physical region descriptor (prd) table address is an i/o register. the descriptor table must be doubleword aligned and must not cross a 64k byte boundary in memory. rw i/o register secondary channel status offset 0ah bit name default description access type
224 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.7.1 function 3 pci configuration space header power management: vendor id function 3 offset 01h ? 00h bit name default description access type 15-0 0001000000100010 the vendor id register contains the value 1022h. ro power management: device id function 3 offset 03h ? 02h bit name default description access type 15-0 0111010000001011 the device id register contains the value 740bh. ro power management: command function 3 offset 05h ? 04h bit name default description access type 15-0 0 reserved. always reads 0. power management: status function 3 offset 07h ? 06h bit name default description access type 15 dpe 0 detected parity error. always reads 0. ro 14 sse 0 signalled system error. always reads 0. ro 13 sma 0 signalled master abort. always reads 0. ro 12 rta 0 received target abort. always reads 0. ro 11 sta 0 signalled target abort. always reads 0. ro 10-9 devsel# 01 devsel# timing. always reads 01b (medium. timing) ro 80 data parity detected. always reads 0. ro 7fbb 1 fast back-to-back capable . always reads 1. ro 6udef0 user definable features. always reads 0 . ro 566cap0 66 mhz capable . always reads 0 . ro 4-0 0000 reserved. always reads 0. power management: revision id function 3 offset 08h bit name default description access type 7-0 00000001 silicon revision code. this register indicates the silicon revision code, for instance 01h = revision a, c0 and d2. 03h = d2 and greater. the register ? s value varies with the revision to which the chip belongs. ro power management: programming interface function 3 offset 09h bit name default description 0-state 7-0 00000000 programming interface. this register determines the programming interface used. the value returned by this register can be changed by writing the desired value to pci configuration function 3, offset 61h. ro
chapter 7 registers 225 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.7.2 power management configuration registers power management: sub class code function 3 offset 0ah bit name default description access type 7-0 00000000 sub class code. the value returned by this register can be changed by writing the desired value to pci configuration function 3, offset 62h. ro power management: base class code function 3 offset 0bh bit name default description access type 7-0 00000000 base class code. the value returned by this register can be changed by writing the desired value to pci configuration function 3, offset 63h. ro power management: cache function 3 offset 0ch bit name default description access type 7-0 00000000 cache. always reads 0. rw power management: latency timer function 3 offset 0dh bit name default description access type 7-0 00010110 latency timer. this register contains the default 16h. rw power management: header type function 3 offset 0eh bit name default description access type 7-0 00000000 header type. this register contains the value 00h. ro power management: general configuration function 3 offset 41h bit name default description access type 7pmioen0 i/o enable for acpi i/o base . 0 = disable access to acpi i/o block 1 = allow access to acpi i/o register block rw 6atr 1 acpi timer reset. 0 = (disabled) the timer is allowed to count. 1 = (enabled) cpi is asynchronously cleared at all times . rw 5-4 00 reserved. always reads 0. 3ats 0 acpi timer size select. 0 = 24-bit timer 1 = 32-bit timer rw
226 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 20 reserved. must remain 0 for proper operation. 1stpgnt0 pci stop grant cycle specification. 0 = stop grant cycle detected when address-phase ad[4] = 1 during a pci special cycle 1 = stop grant cycle detected when data-phase ad[31:0] = 0012_0002h during a pci special cycle rw 00 reserved. always reads 0. power management: sci interrupt configuration function 3 offset 42h bit name default description access type 7-4 0 reserved. always reads 0. 3-0 scisel 0 sci interrupt assignment. the value of these bits specifies the legacy pic irq number that is used for acpi defined sci interrupts. when function 0, offset 41, sci2io bit is high, the irq to the pic selected by this register is forced low. rw power management: most previous power state function 3 offset 43h bit name default description access type 7-4 0 reserved . always reads 0. 3sacpfd soff command status for ac power fail detect. 1= a command was sent to pm04 to place the system in soff. 0 = no soff command sent. this bit is powered by vdd_rtc power plane . this is cleared by writing a 1 to it. writing a 0 has no effect. rwc power management: general configuration function 3 offset 41h bit name default description access type bits sci interrupt bits sci interrupt 0000 disabled (default) 1000 irq7 0001 irq1 1001 irq8 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15
chapter 7 registers 227 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 2-0 ppstate 0 previous power state . the default for the lsb depends on the state of the wron# pin at the trailing edge of rst_soft. ro power management: pnp irq select function 3 offset 45h ? 44h bit name default description access type 15-12 0 reserved. always read 0. 11-8 irq2sel 0 this field assigns an irq to pnpirq2, which is ored with the selected irq after the irq enters the part and before the irq goes on to the 8259-based pic see table 78 for irq assignment coding. if registers pm00 + c9h-c7h do not select the pnpirq[2:0] functions, this field has no effect. rw 7-4 irq1sel 0 this field assigns an irq to pnpirq1, which is ored with the selected irq after the irq enters the part and before the irq goes on to the 8259-based pic. see table 78 for irq assignment coding. if registers pm00 + c9h-c7h do not select the pnpirq[2:0] functions, this field has no effect. rw 3-0 irq0sel 0 this field assigns an irq to pnpirq0, which is ored with the selected irq after the irq enters the part and before the irq goes on to the 8259-based pic. see table 78 for irq assignment coding. if registers pm00 + c9h-c7h do not select the pnpirq[2:0] functions, this field has no effect. rw power management: most previous power state function 3 offset 43h bit name default description access type bits effect 000 moff mechanical off 001 soff soft off 010 fon full on 011 reserved 100 reserved 101 c2 stop grant 110 c3 cpu clock stopped 111 pos power on suspend
228 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 78. irq mapping irqsel interrupt selected irqsel interrupt selected 0000 reserved 1000 reserved 0001 irq1 1001 irq9 0010 reserved 1010 irq10 0011 irq3 1011 irq11 0100 irq4 1100 irq12 0101 irq5 1101 reserved 0110 irq6 1110 irq14 0111 irq7 1111 irq15 power management: pnp dma and chip select function 3 offset 47h ? 46h bit name default description access type 15-13 0 reserved. always read 0. 12 cs1ubm 0 pnpcs1# upper mask bit. if this bit is set, bits 10 ? 8 of the i/o address are masked from pnpcs0 decode for i/o cycles. isa bus devices, such as super i/o chips, require an external decoding of sa[15:11] = 0h. this bit can be used to extend the mask to bits 10 ? 0, so that pnpcs1# can be used for external decoding functions. in addition, this bit affects trap status bits pma0[prm4_tmr_sts] and the system inactivity timer status bits pma8[prm4_trp_sts]. if this bit is cleared, masking for pnpcs1# is available for only the eight lsbs, as specified by function 3, offset cc[maskio4] 12 cs0ubm 0 pnpcs0# upper mask bit. if this bit is set, bits 10 ? 8 of the i/o address are masked from pnpcs0 decode for i/o cycles. isa bus devices, such as super i/o chips, require an external decoding of sa[15:11] = 0h. this bit can be used to extend the mask to bits 10 ? 0, so that pnpcs0# can be used for external decoding functions. in addition, this bit affects trap status bits pma0[prm3_tmr_sts] and the system inactivity timer status bits pma8[prm3_trp_sts]. if this bit is cleared, masking for pnpcs0# is available for only the eight lsbs, as specified by function 3, offset cc[maskio3]. 10-9 i rq12_se l 0 pin definition select for irq12. these bits specify the function for the irq12 as follows: rw 8-7 0 reserved. always read 0. bits effect 00 irq12 01 pin disabled to allow irq12 to be controlled by the mouse interrupt. 10 smbalert# input to the system management logic 11 usboc1#, usb over current 1, to the usb controller
chapter 7 registers 229 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 6-4 dmasel 0 pnpdrq and pnpdak# dma channel selection. this field selects the dma channel for the pnp dma pins, pnpdrq and pnpdak#. channel 4 is reserved. i/o mapped power management register, offset cah is required to select the pnpdrq function in order for that pin to be connected to the internal dma controller. i/o mapped power management register, offset cbh is required to select the pnpdak# function in order for that pin to be controlled by the internal dma controller. rw 3cs1m0 pnpcs1# memory space selection. 0 = pnpcs1# is not selected. 1 = pnpcs1# is selected by accesses to the memory addresses specified by programmable memory range monitor 2 specified by function 3, offset d4h and d8h and pci accesses to this range are claimed by AMD-756 peripheral bus controller and converted into isa bus cycles. if the pnpcs1# function is not selected by i/o mapped power management, offset c6h, then this bit has no effect. rw 2cs1is0 pnpcs1# i/o space selection. 0 = pnpcs1# is not selected. 1 = pnpcs1# is selected by accesses to the i/o addresses specified by programmable i/o range monitor 4 specified by function 3, offset c8h and cch and pci accesses to this range are claimed by AMD-756 peripheral bus controller and converted into isa bus cycles. if the pnpcs1# function is not selected by i/o mapped power management, offset c6h, then this bit has no effect. rw 1cs0m0 pnpcs0# memory space selection. 0 = pnpcs0# is not selected. 1 = pnpcs0# is selected by accesses to the memory addresses specified by programmable memory range monitor 1 specified by function 3, offset d0h and d8h and pci accesses to this range are claimed by AMD-756 peripheral bus controller and converted into isa bus cycles. if the pnpcs0# function is not selected by i/o mapped power management, offset c5h, then this bit has no effect. rw 0cs0is0 pnpcs0# i/o space selection. 0 = pnpcs0# is not selected. 1 = pnpcs0# is selected by accesses to the i/o addresses specified by programmable i/o range monitor 3 specified by function 3, offset c8h and cch and pci accesses to this range are claimed by AMD-756 peripheral bus controller and converted into isa bus cycles. if the pnpcs0# function is not selected by i/o mapped power management, offset c5h, then this bit has no effect. rw power management: pnp dma and chip select function 3 offset 47h ? 46h bit name default description access type
230 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information power management: pins latched on the trailing edge of reset function 3 offset 49h ? 48h bit name default description access type 15-14 00 reserved. always reads 0. 13 enide ? enable ide pull-up/down resistors. if this bit is set, the internal pullups/pulldowns for ide bus signals are enabled, which includes pullups on ddatap[15:0], datas[15:0], and pulldowns on ddrqp and ddrqs. if this bit is cleared, the internal pullups/pulldowns for ide bus signals are disabled. the default for this bit is specified by the state of the spkr# input signal during reset. 12 enpci ? enable pci pullup resistors. if this bit is set, the internal pullups for pci bus signals are enabled, which includes pullups on devsel#, frame#, irdy#, pirq[a,b,c,d]#, serr#,stop#, and trdy#. if this bit is cleared, the internal pullups for pci bus signals are disabled. the default for this bit is specified by the state of the spkr# input signal during reset. 11 e nisa enable isa pullup pulldown resistors. if this bit is set, the internal pullups/pulldowns for isa bus signals are enabled, which includes pullups on iochk#, ior#, iow#, irwq[15,14,12:9, 7:3], la[23:17], memr#, memw#, sa[16:0], sbhe#, sd[15:0], smemr#, smemw#, and pulldowns on drq [7:5, 3:0]. if this bit is cleared, the internal pullups/pulldowns for isa bus signals are disabled. the default for this bit is specified by the state of the spkr# input signal during reset. rw 10 rtce n 1 real time clock enable. this bit determines whether an external or internal realtime clock is selected. 0 = (disabled) an external real time clock is selected. 1 = (enabled) the internal real time clock is enabled. note: when the internal real time clock is not selected, target accesses to the real time clock are ignored by the internal logic and passed to the isa bus. also, the internally-gener- ated irq8# cannot become active. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rw 9-6 rp[16:13] 0000 rp[16:13]. these bits are also accessible through the keyboard controller. they are selected by pull ups or pull downs on daddrp[2:0] and dcs1p# at the trailing edge of pwrgd reset. these four bits go to the keyboard controller to be accessed through bits [6:3] of the read-input-port command, which is generated by an i/o write to 64h of c0h followed by an i/o read of 60h). the default for these bits is specified by pull up or pull down resistors on pins the specified. they are latched during the trailing edge of reset (pwrgd for all of them except pwron). rw 5nmlrst normal reset enabled. 1 = a pull up on iochrdy during the rising edge of pwrgd, selects the normal 1.8 millisecond pulse reset pulse. 0 = a pull down on iochrdy during the rising edge of pwrgd, selects fast reset. used only for simulations and production test. not intended for use in target systems. rw 40 reserved. 3kbde keyboard disable. 0 =disable the internal keyboard controller, the external keyboard controller is selected and the ka20g, kbrc#, ekirq1, and ekirq12 pin functions are selected. 1 = enable the internal keyboard controller, a pull up on rom_kbcs# selects the internal keyboard controller on the trailing edge of pwrgd reset; thus, the kbck, kbdt, msck, and msdt pin functions are selected. rw
chapter 7 registers 231 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 2ps2e 1 ps/2 enable. 0 = disable internal ps/2 mouse 1 = enable internal ps/2 mouse. rw 1-0 0 reserved. (always reads 0) power management: serial irq control function 3 offset 4ah bit name default description access type 70 reserved rw 6contmd0 contmd. this bit selects the serial irq logic to be in quiet or continuous mode. in quiet mode, start frames are initiated by external slave devices. in continuous mode, the start frame is initiated immediately following each stop frame. 0 = quiet mode 1 = continuous mode rw 5-2 frames 0000 frames. these bits select the number of 3-clock irq frames that the logic will generate during a serial irq cycle before issuing the stop frame. rw 1-0 startclks 0 start clocks. this bit specifies the number of clocks wide the start pulse over serirq is during the start frame of a serial irq cycle (including the slave cycle if in quiet mode). rw power management: pins latched on the trailing edge of reset function 3 offset 49h ? 48h bit name default description access type bits number of frames bits number of frames 0000 17 1000 25 0001 18 1001 26 0010 19 1010 27 0011 20 1011 28 0100 21 1100 29 0101 22 1101 30 0110 23 1110 31 0111 24 1111 32 bits number of clocks 00 4 (default) 01 6 10 8 11 reserved
232 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information each of the bits in the prdy timer control register controls the ability of the prdy input signal to disable the AMD-756 controller counters. when prdy becomes active then the counters that correspond to the set bits in this register stop counting until prdy becomes inactive. the counters are disabled without glitches on clocks that may cause unpredictable behavior. if the prdy function of the keylock pin is not selected by i/p mapped power management, offset cdh, then this register has no effect. power management: prdy timer control function 3 offset 4ch bit name default description access type 7-5 0 reserved. always reads 0. 4 acpid 0 acpid. acpi power management timer disable. acpi power management timer specified by i/o mapped power management, offset 08h is disabled while prdy is active. 0 = enabled 1 = disabled rw 3sitd 0 sitd. system inactivity timer disable. system inactivity timer specified by i/o mapped power management, offset 98h is disabled from counting while prdy is active. 0 = enabled 1 = disabled rw 20 reserved. must remain 0 for proper operation. rw 1rtcd0 rtcd. real time clock disable. real time clock ? s counters that are clocked off of the 32 khz clock are disabled from counting while prdy is active. 0 = enabled 1 = disabled rw 0pitd x pitd. programmable interval timer disable. the clock to all three timers of the internal 8254- compatible pit are disabled when prdy is active. 0 = enabled 1 = disabled rw
chapter 7 registers 233 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power management: square wave generation function 3 offset 4eh bit name default description access type 7-4 0 reserved . always reads 0. 3-0 0 sqwave. square wave frequency control. when pm00 +d0h selects the square wave output function, this field is used to specify the frequency of the square wave output on the intirq8# pin. the square wave output is generated by dividing down the 32 khz. clock. here is how this field is decoded: rw power management: power state pin control function 3 offset 53h - 50h bit name default description access type 31 apicen 0 apic interrupt message bus picclk enable during pos state. if this bit is set, the operation of the picclk during the pos state is allowed to continue. if this bit is cleared, picclk is driven low after the stop-grant cycle while going into the pos suspend state. the picclk starts clocking again as soon as the resume event is detected. 30-29 0 reserved. these bits must remain 0 for proper operation. rw 28 tthen 0 tth enable. thermal throttling enable . 0 = disabled 1 = (enabled) (and if i/o mapped power management, offset c2h selects the therm# function for the pin, and the output of the gpio2 input path is high), then thermal throttling (duty cycle specified by the tth_ratio field) is enabled. thermal throttling has absolute priority over normal throttling (see i/o mapped power management, offset 10h); but it will not be invoked if the system is in c2, c3, pos, or soff. rw bits frequency (hz) bits frequency (hz) 0000 output low 1000 256 0001 32768 1001 128 0010 1638 4 1010 6 4 0011 8192 1011 32 0100 4096 1100 16 0101 2048 1101 8 0110 1024 1110 4 0111 512 1111 2
234 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 27-25 tth_ratio 000 thermal throttle ratio. thermal throttling duty cycle. these bits specify the duty cycle of the stpclk# signal to the cpu when the system is in thermal throttling mode (initiated by the therm# pin when enabled by tth_en). the field is decoded as follows: rw 24 pitrsml 0 pit enable. 1 = pit will not generate irq0 to the pic while in pos. this is necessary for timer tick events from resuming the system while in pos. 0 = pit will generate timer tick interrupts to the the pic while in pos.. rw 23 crst_posen 0 crst_pos enable. 0 = (disabled) cpurst# is not asserted during the transition. 1 = (enabled) the assertion of cpurst# during the transition from pos to fon is enabled. this bit must not be set unless the corresponding susp_pose (see below) bit is set (i.e., cpu resets are only allowed if suspend# gets asserted). rw 22 susp_posen 0 susp_pos enable. 0 = (disabled) suspend# is always high. 1 = (enabled) suspend# is asserted during the pos state. this bit has no effect if the i/o mapped power management, offset c4h does not select the suspend# function. rw 21 slpp_posen 0 slpp_pos enable. 0 = (disabled) cpusleep# is always high. 1= (enabled) cpusleep# assertion to the cpu during the pos state is enabled. this bit has no effect if the i/o mapped power management, offset c5h does not select the cpusleep# function. rw 20 pstp_posen 0 pstp_pos enable. 0 = (disabled) pcistop# is always high. 1 = (enabled) pcistop# assertion to the external pll during the pos state is enabled. this bit has no effect if the i/o mapped power management, offset c7h does not select the pcistop# function. rw power management: power state pin control (continued) function 3 offset 53h - 50h bit name default description access type ratio bits description 000 reserved 001 12.5% stpclk# active 010 25.0% stpclk# active 011 37.5% stpclk# active 100 50.0% stpclk# active 101 62.5% stpclk# active 110 75.0% stpclk# active 111 87.5% stpclk# active
chapter 7 registers 235 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 19 c stp_pose n 0 cstp_pos enable. 0 = (disabled) cpustop# is always high. 1 = (enabled) cpustop# assertion to the external pll during the pos state is enabled. this bit has no effect if the i/o mapped power management, offset c6h register does not select the cpustop# function. rw 18 pose n 0 pos enable. 0 = (disabled) stpclk# will not be asserted during the pos state. 1 = (enabled) stpclk# assertion during the pos state is enabled. this bit must be set high for any other bit in this byte register to function (i.e., if stpclk# is not asserted for pos, then none of the other power management control signals can be asserted for pos). rw 17 dcst_posen 0 dcst_pos enable. 0 = (disabled) dcstop# is always high. 1 = (enabled) dcstop# assertion to the dram controller during the pos state is enabled. this bit has no effect if the i/o mapped power management, offset c9h register does not select the dcstop# function. rw 16 zz_posen 0 zz_pos enable. 0 = (disabled) cache_zz is always low. 1 = (enabled) cache_zz assertion to the l2 cache during the pos state is enabled. this bit has no effect if the i/o mapped power management, offset c8h register does not select the cache_zz function. rw 15 crst_c3en 0 crst_c3 enable. 0 = (disabled) cpurst# is not asserted during the transition. 1 = (enabled) the assertion of cpurst# during the transition from c3 to fon is enabled. it is not legal to set this bit unless the corresponding susp_c3e bit is set (i.e., cpu resets are only allowed if suspend# gets asserted). rw 14 su sp_c3e n 0 susp_c3 enable. 0 = (disabled) suspend# is always high. 1 = (enabled) suspend# assertion during the c3 state is enabled. this bit has no effect if the i/o mapped power management, offset c4h does not select the suspend# function. rw 13 slpp_c3en 0 slpp_c3 enable. 0 = (disabled) cpusleep# is always high. 1 = (enabled) cpusleep# assertion to the cpu during the c3 state. is enabled. this bit has no effect if the i/o mapped power management, offset c5h does not select the cpusleep# function. rw 12 pstp_c3en 0 pstp_c3 enable. 0 = (disabled) pcistop# is always high. 1 = (enabled) pcistop# assertion to the external pll during the c3 state is enabled. this bit has no effect if the i/o mapped power management, offset c7h does not select the pcistop# function. rw power management: power state pin control (continued) function 3 offset 53h - 50h bit name default description access type
236 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 11 c stp_c3en 0 cstp_c3 enable. 0 = (disabled) cpustop# is always high. 1 = (enabled) cpustop# assertion to the external pll during the c3 state is enabled. this bit has no effect if the i/o mapped power management, offset c6h register does not select the cpustop# function. rw 10 c3e n 0 c3 enable. 0 = (disabled) stpclk# will not be asserted during the c3 state. 1 = (enabled) stpclk# assertion during the c3 state is enabled. this bit must be set high for any other bit in this byte register to function (i.e., if stpclk# is not asserted for c3, then none of the other power management control signals can be asserted for c3). rw 9dcst_c3en0 dcst_c3 enable. 0 = (disabled) dcstop# is always high. 1 = (enabled) dcstop# assertion to the dram controller during the c3 state. is enabled. this bit has no effect if the i/o mapped power management, offset c9h register does not select the dcstop# function. rw 8 zz_c3en 0 zz_c3 enable. 0 = (disabled) cache_zz is always low. 1 = (enabled) cache_zz assertion to the l2 cache during the c3 state is enabled. this bit has no effect if the pm00 +c8h register does not select the cache_zz function. rw 7crst_c2en0 crst_c2 enable. 0 = (disabled) cpurst# is not asserted during the transition. 1 = (enabled) the assertion of cpurst# during the transition from c2 to fon is enabled. it is not legal to set this bit unless the corresponding susp_c2e bit is set (i.e., cpu resets are only allowed if suspend# gets asserted). rw 6susp_c2en0 susp_c2 enable. 0 = (disabled) suspend# is always high. 1 = (enabled) suspend# assertion during the c2 state is enabled. this bit has no effect if the i/o mapped power management, offset c4h does not select the suspend# function. rw 5slpp_c2en0 slpp_c2 enable. 0 = (disabled) cpusleep# is always high. 1 = (enabled) cpusleep# assertion to the cpu during the c2 state is enabled. this bit has no effect if the i/o mapped power management, offset c5h does not select the cpusleep# function. rw 4pstp_c2en0 pstp_c2 enable. 0 = (disabled) pcistop# is always high. 1 = (enabled) pcistop# assertion to the external pll during the c2 state is enabled. this bit has no effect if the i/o mapped power management, offset c7h does not select the pcistop# function. rw power management: power state pin control (continued) function 3 offset 53h - 50h bit name default description access type
chapter 7 registers 237 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the first three bytes of this register specify the output pins to be controlled to enter and exit the c2, c3, and power on suspend (pos) states; each byte provides the enables for each of these three low-power states. c2 is defined by the enables in bits[7:0], c3 is defined by the enables in bits [15:8], and pos is defined by the enables in bits[23:16]. the fourth byte provides automatic thermal throttling based on cpu over-temperature detection. 3cstp_c2en0 cstp_c2 enable. 0 = (disabled) cpustop# is always high. 1 = (enabled) cpustop# assertion to the external pll during the c2 state is enabled. this bit has no effect if the i/o mapped power management, offset c6h register does not select the cpustop# function. rw 2c2en 0 c2 enable. 0 = (disabled) stpclk# will not be asserted during the c2 state. 1 = (enabled) stpclk# assertion during the c2 state is enabled. this bit must be set high for any other bit in this byte register to function (i.e., if stpclk# is not asserted for c2, then none of the other power management control signals can be asserted for c2). rw 1dcst_c2en0 dcst_c2 enable. 0 = (disabled) dcstop# is always high. 1 = (enabled) dcstop# assertion to the dram controller during the c2 state is enabled. this bit has no effect if the i/o mapped power management, offset c9h register does not select the dcstop# function. rw 0 zz_c2en 1 zz_c2 enable. 0 = (disabled) cache_zz is always low. 1 = (enabled) cache_zz assertion to the l2 cache during the c2 state is enabled. this bit has no effect if the i/o mapped power management, offset c8h register does not select the cache_zz function. rw power management: power state pin control (continued) function 3 offset 53h - 50h bit name default description access type
238 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information power management: pci edge or level select function 3 offset 54h bit name default description access type 7-4 0 reserved. always reads 0. rw 3 edgepid 0 edge triggered interrupt select for pci interrupt d. this bit controls the polarity of the pci interrupt pin pirq[d]#. 0 = pirq[d] is active low and level triggered, which is the normal pci-compliant mode. 1= pirq[d] active high and edge triggered, which is not compliant with pci, but is typical of isa interrupts. rw 2edgepic edge triggered interrupt select for pci interrupt c. this bit controls the polarity of the pci interrupt pin pirq[c]#. 0 = pirq[c] is active low and level triggered, which is the normal pci-compliant mode. 1= pirq[c] active high and edge triggered, which is not compliant with pci, but is typical of isa interrupts. rw 1 edgepib 0 edge triggered interrupt select for pci interrupt b. this bit controls the polarity of the pci interrupt pin pirq[b]#. 0 = pirq[b] is active low and level triggered, which is the normal pci-compliant mode. 1= pirq[b] is active high and edge triggered, which is not compliant with pci, but is typical of isa interrupts. rw 0edgepa0 edge triggered interrupt select for pci interrupt a. this bit controls the polarity of the pci interrupt pin pirq[a]#. 0 = pirq[a] is active low and level triggered, which is the normal pci-compliant mode. 1= pirq[a] active high and edge triggered, which is not compliant with pci, but is typical of isa interrupts. rw power management: pci irq routing function 3 offset 57h ? 56h bit name default description access type 15-12 pirqdsel 0 pirqd# select. these bits map the pciirqd# pin to the internal isa-bus compatible interrupt controller. this field is decoded as shown in table 78. rw 11-8 piirqcsel 0 pirqc# select. these bits map the pciirqc# pin to the internal isa-bus compatible interrupt controller. this field is decoded as shown in table 78. rw 7-4 pirqbsel 0 pirqb# select. these bits map the pciirqb# pin to the internal isa-bus compatible interrupt controller. this field is decoded as shown in table 78. rw 3-0 pirqasel 0 pirqa# select. these bits map the pciirqa# pin to the internal isa-bus compatible interrupt controller. this field is decoded as shown in table 78. rw power management: system management i/o space pointer function 3 offset 5bh ? 58h bit name default description access type 31-16 0 reserved. must remain 0 for proper operation. rw 15-8 11011101 pmbase. these bits specify the pci address bits[15:8] of the 256-byte block of i/o-mapped registers used for system management (address space i/o mapped power management). access to this address space is enabled by function 3 offset 41 bit 7 [pmioen]. rw 7-0 00000001 pm base lsb. always reads 01h ro
chapter 7 registers 239 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power management: system management class code function 3 offset 63h ? 60h bit name default description access type 31-8 ccwrite 0 ccwrite. writes to this register are latched and stored so that they can be read from the classcode field of function 3, offsets 0bh-09h . rw 7-0 0 reserved. must remain 0 for proper operation. rw power management: serial port trap address function 3 offset a3h ? a0h bit name default description access type 31-16 addrcb 00000010 01111000 addrcb. address for the comb trap event (default 0278h). function 3, offset a0 along with function 3, offset a4 define the address for coma and comb trap events. these events can be used to generate an smis or scis, load the associated re- trigger timers (i/o mapped power management, offset 58h and offset 5ch), load the system inactivity timer, or load the burst timers. rw 15-0 addrca 00000011 11111000 addrca. address for the coma trap event. (default 03f8h). rw power management: serial port trap mask function 3 offset a7h ? a4h bit name default description access type 15 ? 8 maskcb 00001111 maskcb. mask for the comb trap event (default 0fh). rw 7-0 maskca 00001111 maskca. mask for the coma trap event. (default 0fh). rw power management: audio port 2 and 1 trap address function 3 offset abh ? a8h bit name default description access type 31-16 addraud2 00000011 00110000 addraud2 . address for the audio trap event #2 (default 0330h). rw 15 ? 0addraud1 00000010 00100000 addraud1. address for the audio trap event #1 (default 0220h). function 3, offset a8, function 3, offset ac, and function 3, offset b0 combine to define the audio trap event. this event can be used to generate an smis or scis, load the associated re-trigger timer (i/o power management, offset 60h), load the system inactivity timer, or load the burst timers. rw power management: audio port 4 and 3 trap address function 3 offset afh ? ach bit name default description access type 31-16 addraud4 00000011 10001000 addraud4. address for the audio trap event #2 (default 0388h). rw 15-0 addraud3 00000101 00110000 addraud3. address for the audio trap event #1 (default 0530h). rw
240 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information , power management: audio port trap mask function 3 offset b3h ? b0h bit name default description 0-state 31-24 maskaud4 00000111 maskaud4. mask for the audio trap event #4 (default 07h). rw 23-16 maskaud3 00000111 maskaud3. mask for the audio trap event #3 (default 07h). rw 15-8 maskaud2 00000001 maskaud2. mask for the audio trap event #2 (default 01h). rw 7-0 maskaud1 00001111 maskaud1. mask for the audio trap event #1 (default 0fh). rw power management: pcmcia 1 and 2 i/o trap address function 3 offset b7h ? b4h bit name default description access type 31-16 addrpio2 00000000 00000000 addrpio2. address for the pcmcia trap event #2 (default 0000h). function 3, offset b4h, function 3, offset b8h, function 3, offset bch, and function 3, offset c0h combine to define the address for the pcmcia1 and pcmcia2 trap events. these events can be used to generate smis or scis, load the associated re-trigger timers (i/o mapped power management, offset 6ch and offset 70h), load the system inactivity timer, or load the burst timers. rw 15 ? 0addrpio1 00000000 00000000 addrpio1. address for the pcmcia trap event #1 (default 0000h). rw power management: pcmcia trap 1 memory address function 3 offset bbh ? b8h bit name default description access type 31-10 addrpme1 00000000 00000000 000000 addrpme1. memory address for the pcmcia1 trap event. rw 9-0 0 reserved. these bits must remain 0 for proper operation. rw power management: pcmcia trap 2 memory address function 3 offset bfh ? bch bit name default description access type 31-10 addrpme2 00000000 00000000 00 addrpme2. memory address for the pcmcia2 trap event (default 0000h). rw 9-0 0 reserved. these bits must remain 0 for proper operation. rw power management: pcmcia trap mask function 3 offset c3h ? c0h bit name default description access type 31-24 maskpme2 00000000 maskpme2. mask for the pcmcia trap event #2 (default 00h). rw 23-16 maskpme1 00000000 maskpme1. mask for the pcmcia trap event #1(default 00h). rw 15-8 maskpio2 00000000 maskpio2. mask for the pcmcia trap event #2 (default 00h). rw 7-0 maskpio1 00000000 maskpio1. mask for the pcmcia trap event #1 (default 00h). rw
chapter 7 registers 241 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information , power management: i /o range monitor 2 and 1 i/o trap address function 3 offset c7h ? c4h bit name default description access type 31-16 addrio2 00000000 00000000 addrio2. address for the i/o trap event #2 (default 0000h). function 3, offset c4h, function 3, offset c8h, function 3, and offset cch, combine to define the address for the programmable i/o range monitor trap events. these events can be used to generate smis or scis, load the associated re-trigger timers (i/o mapped power management, offset 78h, offset 7ch, offset 80h, and offset 84h), load the system inactivity timer, or load the burst timers. rw 15-0 addrio1 00000000 00000000 addrio1. address for the i/o trap event #1 (default 0000h). rw power management: i/o range monitor 4 and 3 i/o trap address function 3 offset cbh ? c8h bit name default description access type 31-16 addrio4 00000000 00000000 addrio4. address for the i/o trap event #4 (default 0000h). rw 15-0 addrio3 00000000 00000000 addrio3. address for the i/o trap event #3 (default 0000h). rw power management: i/o range monitor trap mask function 3 offset cfh ? cch bit name default description access type 31-24 maskio4 00000000 maskio4. mask for the i/o trap event #4 (default 00h). rw 23-16 maskio3 00000000 maskio3. mask for the i/o trap event #3(default 00h). rw 15-8 maskio2 00000000 maskio2. mask for the i/o trap event #2 (default 00h). rw 7-0 maskio1 00000000 maskio1. mask for the i/o trap event #1 (default 00h) rw power management: memory range monitor trap 1 address function 3 offset d3h ? d0h bit name default description access type 31-8 addrmem1 00000000 00000000 00000000 addrmem1. memory address for the pmemrm1 trap event (default 000000h). rw 7-0 00000000 reserved. these bits must remain 0 for proper operation. rw
242 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.7.3 power management i/o space registers the following power management i/o mapped registers are accessed through function 3 offset 58 base pointer register. throughout this section the i/o mapped power management base register will be referred to as pm00. power management: memory range monitor trap 2 address function 3 offset d3h ? d0h bit name default description access type 31-8 addrmem2 00000000 00000000 00000000 addrmem2. memory address for the pmemrm2 trap event (default 0000h). function 3, offset d0h, function 3, offset d4h, and function 3, offset d8h combine to define the address for the programmable memory range monitor 1 and 2 trap events (pmemrm[1,2]). these events can be used to generate smis or scis, load the associated re-trigger timers (i/o mapped power management, offset 88h and offset 8ch), load the system inactivity timer, or load the burst timers. these trap events occur when the following equations are true: pmemrm1: ad[31:8] + maskmem1 == addrmem1 + maskmem1; pmemrm2: ad[31:8] + maskmem2 == addrmem2 + maskmem2; where ad is the address phase of a pci bus memory cycle, it is not necessary for the cycle to be targeted at the AMD-756. the mask bits for the memory addresses can cover bits ad[23:8]. rw 7-0 00000000 reserved. these bits must remain 0 for proper operation. rw power management: memory range monitor trap mask function 3 offset dbh ? d8h bit name default description access type 31-16 maskmem2 00000000 00000000 maskmem2. mask for the memory range trap event #2 (default 0000h). rw 15-0 maskmem1 00000000 00000000 maskmem1. mask for the memory range trap event #1 (default 0000h). rw
chapter 7 registers 243 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power management: status i/o mapped offset 01h ? 00h bit name default description access type 15 ws 0 wakeup status. this bit is set when the system is in the pos state and an enabled resume event occurs as defined in pm00 +16h. upon setting this bit, the system automatically transitions from the pos state to the normal working state (from c3 to fon for the processor). rwc 14-12 000 reserved. always reads 0. 11 p bos 0 power button override status. this bit is set when the pwrbtn# input pin is continuously asserted for more than 4 seconds. the setting of this bit resets the pb_sts bit and transitions the system into the soft off state. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 10 rtcs 0 rtc status. this bit is set by hardware when the real time clock generates an alarm interrupt. if the external real time clock is enabled, then this bit is set when extirq8# is asserted. extirq8# is muxed with the slpbtn# pin; the extirq8# function must be selected for the pin to cause the bit to become high. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 9slp 0 sleep button status. when high, indicates that the sleep button slpbtn# has been asserted. the debounce circuitry causes a 12-to-16 millisecond delay from the time the input signal stabilizes until this bit changes. if the gpio debounce circuitry selected by pm00 +c3h is enabled, then the signal will be debounced twice before this bit is set. this bit is reset by rst_s is enabled (pm00 +c3h), then there is an oft and the value of this bit is retained while in the soff state. rwc 8pbs 0 power button status. this bit is set when the pwrbtn# signal is asserted. the debounce circuitry causes a 12- to 16-millisecond delay from the time the input signal stabilizes until this bit changes. if pwrbtn# is held low for more than four seconds, then this bit is cleared and pbor_sts is set, and the system transitions into the soft off state. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 7-6 0 reserved. always reads 0. 5gs 0 global status. this bit is set by hardware when pm00 +2c bit[bios_rls] is set (typically by an smi routine to release control of the sci/smi lock). if enabled by pm00 +02 bit[gbl_en], this can be used to generate an sci/smi interrupt. rwc 4bms 0 bus master status. this bit is set by hardware when either frame# or bmreq# becomes active, or any internal pci master requests the pci bus, based on the state of the pm00 +cch selection register-while in the c3 power state active. rwc 3-1 000 reserved . always reads 0. 0tms 0 timer carry status. this bit is set when the 23rd (or 31st) bit of the 24-bit (or 32-bit) acpi power management timer pm00 +08h changes. rwc
244 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information the bits in this register are set only by hardware and can be reset by software by writing a one to the desired bit position. the bits in this register correspond to the bits in the power management status register at function 3, offset 01h ? 00h. power management: enable i/o mapped offset 03h ? 02h bit name default description access type 15-11 0 reserved. always reads 0. 10 rtc_en 0 rtc enable. this bit can be set to trigger either an sci or an smi, depending on the setting of register pm00 +04h, [sci_en] bit 0 when register pm00, [rts_sts] bit 10 is set high. rw 9slpbtn_en0 sleep button sci/smi enable. this bit can be set to generate either an sci or an smi, depending on the state of register pm00 +0h4, bit[sci_en] when register pm00, [slpbtn_sts] is set high. rw 8pb_en 0 power button sci/smi enable. this bit can be set to trigger either an sci or an smi, depending on the state of register pm00 +0h4, [sci_en] bit 0 when pm00[pwrbtn_sts] is set high. rw 7-6 0 reserved. always reads 0. 5gbl_en0 global sci/smi enable. this bit can be set to generate either an sci or an smi, depending on the state of pm00 +04h[sci_en] bit 0 when pm00[gbl_sts] is set high rw 4-1 0 reserved. always reads 0. 0tmr_en0 acpi timer enable. this bit can be set to generate either an sci or an smi, depending on the state of pm00 +04 [sci_en] bit 0 when pm00[tmr_sts] bit 0 is set high. rw
chapter 7 registers 245 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power management: control i/o mapped offset 05h ? 04h bit name default description access type 15-14 00 reserved. always reads 0. 13 se 0 sleep enable. reads from this bit always return zero. writing a one to this bit causes the system to sequence into the sleep state defined by the sleep_type field, bits 12 ? 10. wo 12-10 000 sleep type. rw 9-3 0 reserved . always reads 0. 2gbl_rls0 global release. this bit is set by acpi software to indicate the release of the sci/smi lock. when this bit is set, hardware automatically sets the pm28[bios_sts] bit. gbl_rls is cleared by hardware when the bios_sts bit is cleared by software. 0 = disabled 1 = enabled rw 1bmr 0 bus master reload. this bit is used to enable the occurrence of a bus master request to transition the processor from the c3 state to the fon state. 0 = disabled 1 = enabled rw 0sci_en0 sci enable. this bit determines whether a power management event generates an sci or smi. 0 = generate smi, to execute platform specific software. 1 = generate sci, mapped to a traditional interrupt via function 3 offset 42h and used by the operating system. rw bits sleep state setting 000 soft off (also called suspend to disk). the vdd3 power plane is turned off while the vdd-soft and vdd-rtc (vbat) planes remain on. 001 reserved 010 reserved 011 reserved 100 power on suspend. all power planes remain on but the processor is put into the c3 state. system context is maintained. system transitions into specified pos state potentially including all c3 clock controls and assertion of the suspend# signal. 101 normal mode. software can place this field into this state before entering one of the clock controlled states (c2 or c3) to store the system state for resume. this does not cause any action by the hardware. 110 reser ved 111 reser ved
246 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information this is either a 24- or a 32-bit counter, based on the state of register in function 3 offset 41 bit 3. the timer is a free-running up counter that is clocked off of a 3.579545 mhz clock. it does not count when in the system is in soff. when the msb toggles (either bit[23] or bit[31]) then a power management event is generated. refer to pm00[tmr_sts] and pm00 +02 bit[tmr_en]. power management: acpi timer i/o mapped offset 0bh ? 08h bit name default description access type 31-24 etm_val 00000000 extended timer value. when register in function 3 offset 41 bit 3 is high, these are the 8 msbs of the acpi power management timer. when bit 3 is low, this field always reads back as all zeros. rw 23-0 tmr_val 00000000 00000000 00000000 timer value. this field returns the running count of the power management timer. the timer is reinitialized to zero during a reset and continues counting until the 14.31818 mhz input to the chip is stopped. ro
chapter 7 registers 247 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 7.7.4 processor power management registers power management: cpu clock control i/o mapped offset 13h ? 10h bit name default description access type 31-5 0 reserved . always reads 0. 4nht_en0 normal throttling enable. when high, normal throttling (duty cycle specified by bits [3:1]) is enabled. normal throttling is lower priority than thermal throttling (as specified by function 3 offset 50); when thermal throttling is enabled, the throttling duty cycle is specified by function 3 offset 50. throttling is disabled when in the c2, c3, pos, or soff states. when bit 4 is low, normal throttling is disabled. if stpclk# = high, system is running. if stpclk# = low; system is in the c3 state. 0 = stpclk# normal 1 = stpclk# throttled rw 3-1 nht_dty 000 normal throttling duty cycle. this 3-bit field determines the duty cycle of the stpclk# signal when the system is in normal throttling mode. rw 00 reserved. always reads 0. bits stpclk# duty cycle 000 reserved 001 12.5% active 010 25% active 011 37.5% active 100 5 0% active 101 62.5% active 110 75% active 111 87.5% active power management: processor level 2 i/o mapped offset 14h bit name default description access type 7-0 p_lvl2 00000000 processor level 2 register. reads from this register put the processor into c2 power state by asserting stpclk# to suspend the processor. reads from this register return 00h. writes to this register have no effect. wakeup from the stop clock state is done by returning from an interrupt (intr, smi, pwrbtn#, rtc wakeup, or when the sci pin toggles). ro
248 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information power management: processor level 3 i/o mapped offset 15h bit name default description access type 7 p_lvl3 00000000 processor level 3 register. reads from this register put the processor in the c3 clock state with the stpclk# signal asserted. reads from this register return 00h. writes to this register have no effect. wakeup from the stop clock state is done by returning from an interrupt (intr, smi, pwrbtn#, rtc wakeup, or when the sci pin toggles). ro power management: resume event enable i/o mapped offset 17h-16h bit name default description access type 15 0 reserved. always reads 0. 14 rs14 0 resume on assertion of ri#. setting pm00 +28 bit [ri_sts]; this bit does not get set unless the ri# function is selected by pm00 +cia. rw 13-11 000 reserved. always reads 0. 10 rs10 0 resume on system inactivity timer time out. setting pm00 +28h bit [sit_sts]. rw 9rs9 0 resume on assertion of irq8#. setting pm00 [rtc_sts]; regardless whether the rtc is internal or external. rw 8rs8 0 resume on assertion of an unmasked irq. when either bit of intr[1:0] to the cpus is set. rw 7rs7 0 resume on usb-defined resume event. setting pm00 +24 bit [usb_rsm_sts]. rw 6rs6 0 resume on the assertion of the slpbtn#. setting pm00 [slpbtn_sts]; this bit is not set unless the slpbtn# function is selected by pm00 +c3h. rw 5rs5 0 resume on assertion of smbalert#. this function is disabled if the smbalert# function of the irq12 pin is not enabled by function 3 offset 46[irq12_sel]. rw 4rs4 0 resume on an smbus master access to the smbus host slave address. setting pm00 +e0h bit [hslv_sts]. rw 3rs3 0 resume on an smbus access match to the snoop address. setting pm00 +e0h bit [snp_sts]. rw 2rs2 0 resume on assertion of extsmi# . setting pm00 +28h bit[extsmi_sts]; this bit is not set unless the extsmi# function is selected by pm00 +cch. rw 1rs1 0 resume on assertion of pme#. setting pm00 +28h bit[pme_sts]. rw 0rs0 0 resume on assertion of pwrbtn#. setting pm00 bit[pwrbtn_sts] 0 = no action 1 = resume on specified event. rw
chapter 7 registers 249 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power management: flag write i/o mapped offset 18h bit name default description access type 15-0 fwrdata 00000000 00000000 flag write data. writes to this register are passed to the isa data bus to be latched by external ? 373- like devices with the flagwr pin. the sa and sd isa bus pins are valid at least 30 nanoseconds before and 20 nanoseconds after flagwr is asserted such that (1) if a given data bit is not changing, then there will be no glitches on the output of the latch for that bit and (2) if a given data bit is changing, then there will be only one edge on the output of the latch for that signal. reads provide the last data written to this register (internally latched). do not read from pm00 +18h and pm00 +1ah in a single 4-byte cycle. the two registers must be read separately with 2-byte cycles. to use the flagwr pin, pm00 +cah must be set up for the flagwr function. rw power management: flag read i/o mapped offset 1ah bit name default description access type 15-0 frddata 0000000 0 flag read data. reads to this register are passed to the isa data bus to be driven by external ? 244-like devices with the flagrd# pin. it follows the same logical timing as the ior# signal. do not read from pm00 +18h and pm00 +1ah in a single 4-byte cycle. the two registers must be read separately with 2-byte cycles. to use the flagrd# pin, pm00 +cbh must be set up for the flagrd# function. ro power management: soft logic test i/o mapped offset 1ch bit name default description access type 7-1 processor level 2 0 test bits [7:1]. to be determined. rw 00 test bit 0. speed up slow counter. when set, the slow counter that is used to generate the clocks for several functions are replaced with the clock derived from rtcx_in. these include the four clocks to the pm00 +dch blink clock generator, the clocks to all the debounce circuits, the four clocks to the system inactivity timer, and the clock to the power-button override counter. these bits are reset by rst_soft and their value is retained while in the soff state. rw power management: acpi gp status register i/o mapped offset 20h 15 usb_rsm _sts 0 usb resume event status. 0 = no activity 1 = indicates a usb-defined resume event has occurred. this may occur while the system is in the soff power state. this bit is reset by rst_soft and its value is retained in the soff state. 4 14 ri_sts 0 ring indicator pin status. the bit is set when the ri# pin is asserted (active state is dependent upon the gpio14 input polarity). rwc 13-11 0 reserved. always reads 0. 10 t h_sts 0 thermal pin status. the bit is set when the therm# pin is asserted (active state is dependent upon the gpio2 input polarity). the latch that drives this bit is the same as the gpio2 input-path latch. rwc
250 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 9 extsmi_s ts 0 external smi pin status. the bit is set when the extsmi# pin is asserted (active state is dependent upon the gpio12 input polarity). because the circuit that drives this bit is the same as the gpio12 input-path latch it is possible to use polarity control or the debounce function. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 8pme_sts0 pme pin status. the bit is set when the pme# pin is asserted low. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 7-6 0 reserved. always reads 0. 5sit_sts0 system inactivity timer (sit) timeout status. the bit is set by the hardware when the system inactivity timer times out. rwc 4-0 0 reserved. always reads 0. power management: acpi gp status register i/o mapped offset 20h power management: acpi interrupt enable i/o mapped offset 23h ? 22h bit name default description access type 15 0 reserved. always reads 0. 14 rie 0 ring indicator enable. this bit enables the ri# pin to signal acpi interrupts. 0 = disabled 1 = enabled rw 13-11 0 reserved. always reads 0. 10 th e 0 therm enable. this bit enables the therm# pin to signal acpi interrupts. 0 = disabled 1 = enabled rw 9smie0 external smi enable. this bit enables the smi# pin to signal acpi interrupts. 0 = disabled 1 = enabled rw 8pmei0 pme enable. this bit enables the pme# pin to signal acpi interrupts. 0 = disabled 1 = enabled rw 7-6 0 reserved. always reads 0. 5site 0 system inactivity timer enable. 0 = disabled 1 = enabled rw 4-0 0 reserved. always reads 0. power management: lpt-usb event status i/o mapped offset 24h bit name default description access type 7lpt3_sts0 lpt3 status. 0 = no activity 1 = indicates access to i/o space in the range 3bch-3bfh. rwc 6lpt2_sts0 lpt2 status. 0 = no activity 1 = indicates access to i/o space in the range 278h-27fh. rwc
chapter 7 registers 251 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 5lpt1_sts0 lpt1 status. 0 = no activity 1 = indicates access to i/o space in the range 378h-37fh. rwc 4 usb_rsm 0 usb resume event status. 0 = no activity 1 = indicates a usb-defined resume event has occurred. this may occur while the system is in the soff power state. this bit is reset by rst_soft and its value is retained in the soff state. rwc 3usb_blk0 usb bulk transfer status. 0 = no activity 1 = indicates a usb bulk transfer has occurred rwc 2usb_int0 usb interrupt transfer status. 0 = no activity 1 = indicates a usb interrupt transfer has occurred rwc 1 usb_iso 0 usb isochronous transfer status. 0 = no activity 1 = indicates a usb isochronous transfer has occurred rwc 0usb_ctl0 usb control transfer status. 0 = no activity 1 = indicates a usb isochronous transfer has occurred rwc power management: lpt-usb event interrupt enable i/o mapped offset 25h bit name default description access type 7lpt3_en0 lpt3 interrupt enable. 0 = disabled 1 = enabled rw 6lpt2_en0 lpt2 interrupt enable. 0 = disabled 1 = enabled rw 5lpt1_en0 lpt1 interrupt enable. 0 = disabled 1 = enabled . rw 4 usb_rsm 0 usb resume event interrupt enable. 0 = disabled 1 = enabled . rw 3usb_blk0 usb bulk transfer interrupt enable. 0 = disabled 1 = enabled . rw 2usb_int0 usb interrupt transfer interrupt enable. 0 = disabled 1 = enabled . rw 1 usb_iso 0 usb isochronous transfer interrupt enable. 0 = disabled 1 = enabled . rw 0usb_ctl0 usb control transfer interrupt enable. 0 = disabled 1 = enabled . rw power management: lpt-usb event status i/o mapped offset 24h bit name default description access type
252 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information power management: power supply control i/o mapped offset 27h ? 26h bit name default description access type 15 usb_rsm 0 usb resume event interrupt enable. 0 = disabled 1 = enabled . rw 14 ri_c tl 0 ring indicator control. this bit controls the ri# input pin used to trigger power plane control. 0 = (disabled) pm00 +28h bit[ri_sts] does not affect the state of the pwron# pin. 1 = enables the pm00 +28h bit[ri_sts]-set-to-high event to be used as a trigger to set the pwron# output pin into the active state. rw 13 sbod 0 sleep button override disable. 0 = (enabled) the power button override event from the slpbtn# pin is enabled to place the system into the soff mode. 1 = (disabled) the power button override event from the slpbtn# pin (holding slpbtn# active for four seconds) will not automatically transition the system into soff. rw 12 slpbtn_ctl 0 sleep button control. this bit enables the slpbtn# input pin to trigger power plane control. 0 = (disabled) the pm00 bit [slpbtn_sts] does not affect the state of the pwron# pin. 1 = (enabled) the pm00 bit [slpbtn_sts] set-to-high event can be used as a trigger to set the pwron# output pin into the active state. rw 11 p bod 0 power button override disable. 0 = (enabled) the power button override event is enabled to place the system into the soff mode. 1 = (disabled) the power button override event (holding pwrbtn# active for four seconds) will not automatically transition the system into soff. rw 10 p me_ctl 0 pme control. this bit enables the pme# input pin (pci power management event) to trigger power plane control. 0 = (disabled) pm00 +28h bit [pme_sts] does not affect the state of the pwron# pin. 1 = (enabled) the pm00 +28h bit [pme_sts]-set-to-high event can be used as a trigger to set the pwron# output pin into the active state. rw 9pb_ctl0 power button control (rw). this bit enables the power button used to trigger power plane control. 0 = (disabled) the pm00 bit [pwrbtn_sts] does not affect the state of the pwron# pin. 1 = (enabled) the pm00 bit [pwrbtn_sts] set-to-high event can be used as a trigger to set the pwron# output pin into the active state. rw 8rtc_ps_ctl0 real time clock alarm power control. this bit enables the real time clock alarm used to trigger power plane control. 0 = (disabled) the pm00 bit [rtc_sts] does not affect the state of the pwron# pin. 1 = (enabled)the pm00 bit [rtc_sts] set-to-high event can be used as a trigger to set the pwron# output pin into the active state. rw 7-4 0000 reserved . always reads 0. 3hslv 0 host slave smbus address match control. this bit enables the smbus host-as-slave address match used to trigger power plane control. 0 = disabled 1 = (enabled) the smbus host-as-slave address match event (pm00 +e0h bit [hslv_sts]) can be used as the trigger to set the pwron# output pin into the active state. rw
chapter 7 registers 253 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the bits in this register are used to enable a corresponding trigger that will set pwron# into the active state. thus, when the specified trigger occurs, pwron# will go low to power up most of the system, including the vdd3 power plane of the AMD-756. if pwron# is already low, then these bits will not affect it. this register is reset by rst_soft and when a power button override event occurs. note: the value of this register is retained while in the soff state. 2snp 0 snoop address match control. this bit enables the smbus snoop address match used to trigger power plane control. 0 = disabled 1 = (enabled) the smbus snoop address match event (pm00 +e0h bit[snp_sts]) can be used as the trigger to set the pwron# output pin into the active state. rw 1 usb_rsm 0 usb resume control. this bit enables the usb-defined resume event used to trigger power plane control. 0 = disabled 1 = (enabled) the usb-defined resume event (pm00 +24h bit[usb_rsm_sts]) can be used as the trigger to set the pwron# output pin into the active state. rw 0 extsmi_ctl 0 external smi control. this bit enables the extsmi# pin used to trigger power plane control. 0 = (disabled) pm00 +28h bit [extsmi_sts] does not affect the state of the pwron# pin. 1 = (enabled) the pm00 +28h bit [extsmi_sts] set-to-high event can be used as a trigger to set the pwron# output pin into the active state. rw power management: power supply control i/o mapped offset 27h ? 26h bit name default description access type power management: global smi status i/o mapped offset 29h ? 28h bit name default description access type 15 0 reserved. always reads 0. 14 ri_sts 0 ring indicator pin status. the bit is set when the ri# pin is asserted (active state is dependent upon the gpio14 input polarity). rwc 13-12 0 reserved. always reads 0. 11 smb_sts 0 system management bus event. the bit is set when a smbus event occurs, including the completion of the current smbus host access, host-as-slave access, slave detect access, and assertion of smbalert#. the status bits for this register are all the sts suffix bits found in pm00 +e0h and enabled in pm00 +e2h. rwc 10 th_sts 0 thermal pin status. the bit is set when the therm# pin is asserted (active state is dependent upon the gpio2 input polarity). the latch that drives this bit is the same as the gpio2 input-path latch. rwc
254 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information each of the evt bits (bits[4:2, 0]) specify enabled status bits in other registers. these are not sticky bits. they reflect the combinatorial equation of: xxx_evt = (status1 and enable1) or (status2 and enable2) . . . or (statusx and enablex). 9 extsmi_sts 0 external smi pin status. the bit is set when the extsmi# pin is asserted (active state is dependent upon the gpio12 input polarity). because the circuit that drives this bit is the same as the gpio12 input-path latch it is possible to use polarity control or the debounce function. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 8pme_sts0 pme pin status. the bit is set when the pme# pin is asserted low. this bit is reset by rst_soft and the value of this bit is retained while in the soff state. rwc 7smi_sts0 software smi status). the bit is set when a write of any value is sent to pm00 +2fh. this bit can result in smi interrupts only (if enabled in pm00 +2ah bit[swismi_en]); it cannot be enabled to generate sci interrupts. rwc 6bios_sts0 bios status. the bit is set when the pm00 +04h bit[gbl_rls] is set (by acpi software to indicate the release of the sci/smi lock). bios_sts is cleared when a 1 is written to it; writing a 1 to bios_sts also causes the hardware to clear pm00 +04h bit[gbl_rls]. this bit can result in smi interrupts only (if enabled in pm00 +2ah bit[biossmi_en]); it cannot be enabled to generate sci interrupts. rwc 5sit_sts0 system inactivity timer (sit) timeout status. the bit is set by the hardware when the system inactivity timer times out. rwc 4usb_evt0 usb event status. lpt access or usb transfer or resume event status. this bit is set when any of the bits in pm00 +24h that are enabled in pm00 +25h, go high to indicate a usb transfer or resume event or an lpt access. ro 3gpio_evt0 gpio interrupt status. the bit is set when any of the enabled gpio pin status bits specified by pm00 +d4h become active. o 2pm1_evt0 pm1 event status. the bit is set when any of the enabled power management events specified by pm00 that can cause interrupts to become active. these include pm00 bits [rtc_sts, slpbtn_sts, pwrbtn_sts, gbl_sts, and tmr_sts]. ro 10 reserved. always reads 0. 0 trp_sevt 0 trap smi status. the bit is set when any of the enabled hardware trap status bits specified by pm00 +a8h become active. ro power management: global smi status (continued) i/o mapped offset 29h ? 28h bit name default description access type
chapter 7 registers 255 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information each of these enable bits gates the ability for the status and event bits to generate smi# interrupts. when set, these bits enable the corresponding event to generate an smi interrupt, regardless of the state of pm00 +04 bit[sci_en]. power management: global smi enable i/o mapped offset 2bh ? 2ah bit name default description access type 15 0 reserved. always reads 0. 14 ri_smie 0 ring indicator smi enable. 0 = disabled 1 = enables the pm00 +28h bit [ri_sts] to generate an smi. rw 13 sb_smie 0 sleep button smi enable. 0 = disabled 1 = enables the pm00 +28h bit [slpbtn_sts] to generate an smi. rw 12 pb_smie 0 power button smi enable). 0 = disabled 1 = enables the pm00 +28h bit [pwrbtn_sts] to generate an smi. rw 11 smb_smie 0 sm bus smi enable. 0 = disabled 1 = enables the pm00 +28h bit [smbus_evt] to generate an smi. rw 10 th_smie 0 thermal smi enable. 0 = disabled 1 = enables the pm00 +28h bit [therm_sts] to generate an smi. rw 9ext_smie0 external smi smi enable. 0 = disabled 1 = enables the pm00 +28h bit [extsmi_sts] to generate an smi. rw 8 pme_smie 0 pme smi enable. 0 = disabled 1 = enables the pm00 +28h bit [pme_sts] to generate an smi. rw 7s_smie 0 software smi enable. 0 = disabled 1 = enables the pm00 +28h bit [swi_sts] to generate an smi. rw 6 bios_smie 0 bios smi enable. 0 = disabled 1 = enables the pm00 +28h bit [bios_sts] to generate an smi. rw 5sit_smie0 sit smi enable. 0 = disabled 1 = enables the pm00 +28h bit [sit_sts] to generate an smi. rw 4usb_smie0 usb resume smi enable. 0 = disabled 1 = enables any of the pm00 +28h bits [4:0] bits to generate an smi if enabled by the corresponding bits in pm00 +25h bits [4:0]. rw 3gpio_smie0 gpio smi enable. 0 = disabled 1 = enables the pm00 +28h bit [gpio_evt] to generate an smi. rw 2pm1_smie0 pm1 smi enable. 0 = disabled 1 = enables the pm00 +28h bit [pm1_evt] to generate an smi. rw 10 reserved. must remain 0 for proper operation. rw 0trp_smie0 trap smi enable. 0 = disabled 1 = enables the pm00 +28h bit [trp_evt] to generate an smi. rw
256 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information offsets 40-94 are reserved and should not be written to. power management: global smi control i/o mapped offset 2dh ? 2ch bit name default description access type 15-6 0 reserved. always reads 0. 5smiact0 smi active. if smilk is high, then this bit is set on the leading edge of the smi output. it holds the smi# pin in the active state. rwc 4smilk0 smi lock control. 0 = latching disabled, the smi# pin is controlled solely by the logic prior to smiact. 1 = latching enabled, the smi# pin is locked into the active state, by a latch before the output pad, after it is asserted. the latch is controlled by smiact. rw 3-2 0 reserved. always reads 0. 1bios_rls0 bios sci/smi lock release. this bit is set by software to indicate the release of the sci/smi lock. when this bit is set, pm00 bit[gbl_sts] is set by the hardware. bios_rls is cleared by the hardware when pm00 bit[gbl_sts] is cleared by software. if pm00 +02 bit[gbl_en] is set, then setting this bit will generate an sci or smi interrupt . rw 0smi_en0 bios sci/smi lock release. this bit is set by software to indicate the release of the sci/smi lock. when this bit is set, pm00 bit[gbl_sts] is set by the hardware. bios_rls is cleared by the hardware when pm00 bit[gbl_sts] is cleared by software. if pm00 +02 bit[gbl_en] is set, then setting this bit will generate an sci or smi interrupt . rw power management: software smi trigger i/o mapped offset 2fh bit name default description access type 7-0 smi command 00000000 smi command. reads or writes to this register set pm00+28 bit[swi_sts]. if pm00+2a bit[swi_en] is set, then accesses to this port can be used to generate smi interrupts. reads of this register provide the data last written to it. rw
chapter 7 registers 257 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information power management: system inactivity timer i/o mapped offset 9bh ? 98h bit name default description access type 31-18 0 reserved. always reads 0. 17-16 00 clock source. specifies the clock to the system inactivity timer as in the following table. rw 15-8 00000000 current count. system inactivity timer current count value is read here. ro 7-0 00000000 reload value. writes to this field cause the system inactivity counter to be reloaded with the value placed here. wo power management: hardware trap status bits i/o mapped offset abh ? a8h bit name default description access type 31-20 0 reserved. always read 0. 19 p mm2_sts 0 programmable memory range monitor 2 trap status. 0 = no event 1 = event occurred rwc 18 p mm1_sts 0 programmable memory range monitor 1 trap status. 0 = no event 1 = event occurred rwc 17 p r m 4_ st s 0 programmable range monitor 4 trap status. 0 = no event 1 = event occurred rwc 16 p rm3_sts 0 programmable range monitor 3 trap status. 0 = no event 1 = event occurred rwc 15 prm2_sts 0 programmable range monitor 2 trap status. 0 = no event 1 = event occurred rwc 14 p rm1_sts 0 programmable range monitor 1 trap status. 0 = no event 1 = event occurred rwc 13 usb_sts 0 usb trap status. 0 = no event 1 = event occurred rwc 12 pcmcia2_sts 0 pcmcia2 trap status. 0 = no event 1 = event occurred rwc 11 pcmcia1_sts 0 pcmcia1 trap status. 0 = no event 1 = event occurred rwc 10 k bm_sts 0 keyboard mouse trap status. 0 = no event 1 = event occurred rwc 9vid_sts 0 video trap status. 0 = no event 1 = event occurred rwc 8aud_sts0 audio trap status. 0 = no event 1 = event occurred rwc 7comb_sts0 com b trap status. 0 = no event 1 = event occurred rwc 6coma_sts0 com a trap status. 0 = no event 1 = event occurred rwc bits clock period maximum time (clock x 255) 00 64 msec 16.32 seconds 01 1 sec 255 seconds = 4.25 minutes 10 16 sec 68 minutes = 1.13 hours 11 256 sec 1088 minutes = 18.13 hours
258 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information each of these status bits is driven by a hardware trap detect timer. if the trap occurs, then the status bit is set. each bit is cleared when written with a 1; writing a 0 has no effect. if a status bit is high and its corresponding enable bit is high, it will cause the hardware trap global event bit to go high in pm00 +28h bit[trp_evt]. 5lpt_sts 0 lpt trap status. 0 = no event 1 = event occurred rwc 4fdd_sts0 floppy disk drive trap status. 0 = no event 1 = event occurred rwc 3 dss_sts 0 disk secondary slave trap status. 0 = no event 1 = event occurred rwc 2dsm_sts0 disk secondary master trap status. 0 = no event 1 = event occurred rwc 1dps_sts 0 disk primary slave trap status. 0 = no event 1 = event occurred rwc 0dpm_sts0 disk primary master trap status. 0 = no event 1 = event occurred rwc power management: hardware trap status bits (continued) i/o mapped offset abh ? a8h bit name default description access type power management: hardware trap enable bits i/o mapped offset afh ? ach bit name default description access type 31-20 0 reserved. always read 0. 19 p mm2_en 0 programmable memory range monitor 2 trap enable. 0 = disabled 1 = enabled rw 18 p mm1_en 0 programmable memory range monitor 1 trap enable. 0 = disabled 1 = enabled rw 17 p r m 4_ e n 0 programmable range monitor 4 trap enable. 0 = disabled 1 = enabled rw 16 p rm3_en 0 programmable range monitor 3 trap enable. 0 = disabled 1 = enabled rw 15 prm2_en 0 programmable range monitor 2 trap enable. 0 = disabled 1 = enabled rw 14 p rm1_en 0 programmable range monitor 1 trap enable. 0 = disabled 1 = enabled rw 13 usb_en 0 usb trap enable. 0 = disabled 1 = enabled rw 12 pcmcia2_en 0 pcmcia2 trap enable. 0 = disabled 1 = enabled rw 11 pcmcia1_en 0 pcmcia1 trap enable. 0 = disabled 1 = enabled rw 10 k bm_e n 0 keyboard mouse trap enable. 0 = disabled 1 = enabled rw 9vid_en 0 video trap enable. 0 = disabled 1 = enabled rw 8aud_en0 audio trap enable. 0 = disabled 1 = enabled rw 7comb_en0 com b trap enable. 0 = disabled 1 = enabled rw 6coma_en0 com a trap enable. 0 = disabled 1 = enabled rw 5lpt_en 0 lpt trap enable. 0 = disabled 1 = enabled rw 4fdd_en0 floppy disk drive trap enable. 0 = disabled 1 = enabled rw 3 dss_en 0 disk secondary slave trap enable. 0 = disabled 1 = enabled rw 2dsm_en0 disk secondary master trap enable. 0 = disabled 1 = enabled rw
chapter 7 registers 259 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information each of these bits gates the corresponding bit in the hardware trap status register from generating an interrupt. a high enables the corresponding status bit to generate an interrupt; also, when an enabled hardware event status bit is set, the pm00 +28h bit[trp_evt] bit goes high. a low disables the corresponding status bit. 1dps_en0 disk primary slave trap enable. 0 = disabled 1 = enabled rw 0dpm_en0 disk primary master trap enable. 0 = disabled 1 = enabled rw power management: hardware trap enable bits (continued) i/o mapped offset afh ? ach bit name default description access type power management: hardware trap reload enable for system inactivity timer i/o mapped offset b3h ? b0h bit name default description access type 31-22 0 reserved. always read 0. 21 bm_req 0 bus master request inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 20 ext_smi 0 external smi inactivity timer reload enable 0 = disable reload 1 = enable reload rw 19 p mm2_rle 0 programmable memory range monitor 2. inactivity timer reload enable 0 = disable reload 1 = enable reload rw 18 p mm1_rle 0 programmable memory range monitor 1. inactivity timer reload enable 0 = disable reload 1 = enable reload rw 17 p r m 4_ r l e 0 programmable range monitor 4 inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 16 p rm3_rle 0 programmable range monitor 3 inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 15 prm2_rle 0 programmable range monitor 2 inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 14 p rm1_rle 0 programmable range monitor 1 inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 13 usb_rle 0 usb inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 12 pcmcia2_rle 0 pcmcia2 inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 11 pcmcia1_rle 0 pcmcia1 inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 10 k bm_rle 0 keyboard mouse inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 9vid_rle 0 video inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 8aud_rle0 audio inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 7comb_rle0 com b inactivity timer reload enable. 0 = disable reload 1 = enable reload rw
260 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information each of these bits enables reloading of its corresponding inactivity timer. general purpose i/o registers 6coma_rle0 com a inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 5lpt_rle 0 lpt inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 4fdd_rle0 floppy disk drive inactivity timer reload enable. 0 = d i s a b l e r e l o a d 1 = e n a b l e r e l o a d r w 3 dss_rle 0 disk secondary slave inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 2dsm_rle0 disk secondary master inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 1dps_rle0 disk primary slave inactivity timer reload enable. 0 = disable reload 1 = enable reload rw 0dpm_rle0 disk primary master inactivity timer reload enable. 0 = disable reload 1 = enable reload rw power management: hardware trap reload enable for system inactivity timer (continued) i/o mapped offset b3h ? b0h bit name default description access type power management: irq reload enable for inactivity timer i/o mapped offset b7h ? b4h bit name default description access type 31-16 0 reserved. must remain 0 for proper operation. rw 15-0 0 irqs reload the system inactivity timer. each of these bits corresponds to an irq number (e.g., bit[12] corresponds to irq12). the exception to this is bit[2], which corresponds to the logical or of the two intr[1:0] pins. when set, each bit enables the corresponding interrupt signal to cause the system inactivity timer to reload while it is high. for example, if irqrl[9] is high, then while irq9 is high, the system inactivity timer will be held at its reload value. when cleared, bits of this register do not affect the system inactivity time rw power management: gpio direction control (gpio_dir) i/o mapped offset c0h bit name default description access type 70 reserved. always reads 0. 6 ltch_sts 0 latch status. gpio latch status. this bit provides the current state of the latch associated with the input pad for the pin that corresponds to the register. rwc 5rtin 0 real time in. this bit provides the current, not-inverted state of the pad for the pin that corresponds to the register. ro
chapter 7 registers 261 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information registers d1h-c0h all have this same format. there is one single-byte register for each gpio pin. registers pm00 +c3h (associated with slpbtn#) and pm00 +cch (associated with extsmi#) are reset by rst_soft and remain powered when in the soff state (powered by vdd_soft). the other registers are reset by pwrgd and off when in the soff state. 4 debounce 0 debounce. debounce the input signal. 0 = no debounce 1 = the input signal is required to be held active without glitches for 12 to 16 milliseconds before being allowed to set the gpio latch or being capable of being passed along to the circuitry being controlled by the output of the input path. rw 3-2 mode [1:0] 00 mode[1:0]. pin mode select. mode[1] selects between the pin being defined as a gpio function (mode[1] low) or an alternate function (mode[1] high). for gpio pins, mode[0] selects between inputs (mode[0] low) and outputs (mode[0] high). if mode[1] is high, then mode[0] selects between multiple alternate functions for the pins. table 79 below shows the default states for these registers and the pin definitions base on the state of mode[1:0]. the ? default ? field shows the defaults for all the bits in the register. rw 1-0 x[1:0] 00 x[1:0]. if the gpio input path is not used by the pin (e.g. if the function is a gpio function or if it is an configurable input pin like the pnp irqs), then this field does not matter. if the gpio input path is used by the pin, then based on whether this pin is a input or an output (selected by mode also), this register defines i/o modes as described in table 80 below. rw power management: gpio direction control (gpio_dir) (continued) i/o mapped offset c0h bit name default description access type table 79. pin function pin control register default mode function notes gpio[17:0] b00 general purpose input gpio[17:0] b01 general purpose output gpio[0] pm00 +c0h h08 (smbusc) b1x smbusc 3 gpio[1] pm00 +c1h h08 (smbusd) b1x smbusd 3 gpio[2] pm00 +c2h h0c (therm#) b10 pmirq0; gpio input path drives logic b11 therm#; gpio input path drives throttling logic 1 gpio[3] pm00 +c3h h0c (slpbtn#) b10 pmirq1; gpio input path drives logic 3 b11 slpbtn#; gpio input path drives pm logic 1,2 gpio[4] pm00 +c4h h08 (suspend#) b1x suspend# gpio[5] pm00 +c5h h05 (gpio output, high) b10 pnpcs0# b11 cpusleep#
262 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information note 1: the output of the input path for gpio[17, 16, 3, 2] goes to the i/o apic to drive the interrupt request inputs to some of the redirection-table entries. these signals, between the gpio logic and the apic, are not ever disabled, even if the pin ? s function is other-than gpio. note 2: when the slpbtn# function is selected, then the x0 further decodes this input. if pm00 +c3h bits[3:0] = 0ch, then the slpbtn# function is selected; if pm00 +c3 bits[3:0] = 0dh, then the extirq8#, external real time clock interrupt function is selected. extirq8# is passed to the pic logic without going through the gpio input path. note 3: pm00 +c0h, pm00 +c1h, pm00 +c3h, pm00 +cch, and pm00 +ceh are all reset by rst_soft and their values are retained while in the soff state. gpio[6] pm00 +c6h h05 (gpio output, high) b10 pnpcs1# b11 cpustop# gpio[7] pm00 +c7h h05 (gpio output, high) b10 pnpirq0; gpio input path drives pnp logic b11 pcistop# gpio[8] pm00 +c8h h04 (gpio output, low) b10 pnpirq1; gpio input path drives pnp logic b11 cache_zz gpio[9] pm00 +c9h h05 (gpio output, high) b10 pnpirq2; gpio input path drives pnp logic b11 dcstop# gpio[10] pm00 +cah h04 (gpio output, low) b10 pnpdrq 11b flagwr gpio[11] pm00 +cbh h05 (gpio output, high) b10 pnpdak# b11 flagrd# gpio[12] pm00 +cch h0c (extsmi#) b10 bmreq# 3 b11 extsmi#; gpio input path drives pm logic gpio[13] pm00 +cdh h0c (keylock) b10 prdy b11 keylock gpio[14] pm00 +ceh h08 (ri#) b1x ri#; gpio input path drives pm logic 3 gpio[15] pm00 +cfh h04 (gpio output, low) ? b1x c32khz gpio[16] pm00 +d0h h05 (gpio output, high) b10 intirq8# b11 sqwave gpio[17] pm00 +d1h h00 (gpio input) b10 msirq b11 serirq table 79. pin function (continued) pin control register default mode function notes
chapter 7 registers 263 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 80. i/o mode i/o (mode) bit name function input x0 activehi when low, the pin is active low and the signal is inverted as it is brought into the input path; when high the pin is active high and therefore not inverted as it is brought through the input path. input x1 latch when low the latched version of the signal is not selected. when high, the latch output is selected. output x[1:0]=00b output is forced low. output x[1:0]=01b output is forced high. output x[1:0]=10b gpio output clock 0 (specified by pm00 +dc bits[15:0]). output x[1:0]=11b gpio output clock 1 (specified by pm00 +dc bits[31:16]). gpio pin interrupt status bar0 + offset d7h ? d4h bit name default description access type 31-18 0 reserved. must remain 0 for proper operation. rw 17-0 0 gpio status bits. each of these status bits is driven by the output of the input circuit associated with the gpio pins. the latch associated with each gpio input circuit is cleared when the corresponding bit in this register is written with a 1; writing a 0 has no effect. rwc gpio pin interrupt enable bar0 + offset dbh ? d8h bit name default description access type 31-18 0 reserved. must remain 0 for proper operation. rw 17-0 0 gpio enable bits. each of these enable bits gate the ability of the output of the gpio pin input path to generate an interrupt. when these bits are low, the path from the corresponding status bit in pm00 +d4h to the sci/smi interrupts is forced to the inactive state. rw gpio output clock 0 and 1 bar0 + offset dfh ? dch bit name default description access type 31-30 clk1_base 00 clock 1 base. gpio output clock timer base. specifies the clock for the counter that generates the gpio output clock. rw bits clock length 00 250 microseconds (default) 01 2 milliseconds 10 16 milliseconds 11 256 milliseconds
264 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information this register specifies the high time and the low time for the gpio output clocks. these clocks can be selected as the output for any of the gpio pins. these output clocks consist of a 7-bit down counter that is alternately loaded with the high time and the low time. the clock for the counters is selected by clk[1,0]base. 29-23 clk1_hi 0000000 clk 1 high. gpio output clock 1 high time. specifies the high time for the gpio output clocks in increments of the clock specified by clk1 base (if the base is 16 milliseconds, then 0 specifies 16 milliseconds, 1 specifies 32 milliseconds, etc.). 0 = 1 clock 1 = 2 clocks rw 22-16 clk1_lo 000000 clock 1 low. specifies the low time for the gpio output clocks in increments of the clock specified by clk1 base (if the base is 16 milliseconds, then 0 specifies 16 milliseconds, 1 specifies 32 milliseconds, etc.). 0 = 1 clock 1 = 2 clocks rw 15-14 clk 0 base 00 clock 0 base. specifies the clock for the counter that generates the gpio output clock 0. rw 13-7 clk0_hi 0000000 clk 0 high. specifies the high time for the gpio output clocks in increments of the clock specified by clk0 base (if the base is 16 milliseconds, then 0 specifies 16 milliseconds, 1 specifies 32 milliseconds, etc.). 0 = 1 clock 1 = 2 clocks rw 6-0 clk0_lo 0000000 clock 0 low. specifies the low time for the gpio output clock 0 in increments of the clock specified by clk0 base (if the base is 16 milliseconds, then 0 specifies 16 milliseconds, 1 specifies 32 milliseconds, etc.). 0 = 1 clock 1 = 2 clocks rw gpio output clock 0 and 1 bar0 + offset dfh ? dch bit name default description access type bits clock length 00 250 microseconds (default) 01 2 milliseconds 10 16 milliseconds 11 256 milliseconds
chapter 7 registers 265 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information system management bus registers sm bus global status pm00 + offset e1h ? e0h bit name default description access type 15-12 0000 reserved. these bits must remain 0 for proper operation. rw 11 sm_bsy 0 smbus busy. 0 = the smbus is not busy. 1 = the smbus is currently busy with a cycle generated by either the host or another smbus master. ro 10 snba_sts 0 sm bus alert status. this bit is set by the hardware when smbalert# is asserted low. this bit will not be set unless the smbalert# function is selected by function 3, offset 46, bits[10:9]. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2h bit[smba_en] . rwc 9hslv_sts0 host-as-slave address match status. this bit is set by the hardware when an smbus master (including the host controller) generates a smbus write cycle with a 7-bit address that matches the one specified by pm00 +eeh. this bit is not set until the end of the acknowledge bit after the last byte is transferred over the smbus cycle; however, if a time out occurs after the address match occurs and before last acknowledge, then this bit will not be set. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2h bit[hslv_en]. rwc 8snp_sts0 snoop address match status. this bit is set by the hardware when an smbus master (including the host controller) generates an smbus cycle with a 7-bit address that matches the one specified by pm00 +efh. this bit is not set until the end of the acknowledge bit after the last byte is transferred over the smbus cycle; however, if a time out occurs after the address match occurs and before the last acknowledge, then this bit will not be set. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2 bit[snp_en]. rwc 7-6 0 reserved. these bits must remain 0 for proper operation. rw 5to_sts 0 time out error status. this bit is set by the hardware when a slave device forces a time out by holding the smbusc pin low for more than 30 milliseconds. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2h bit[hcyc_en]. rwc 4hcyc_sts0 host cycle complete status. this bit is set by the hardware when a host cycle completes successfully. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2h bit[hcyc_en]. rwc 3hst_sts0 host controller busy. 0 = the smb host controller is not busy. 1 = the smbus host controller is currently busy with a cycle. ro 2prerr_sts0 protocol error status. this bit is set by the hardware when a slave device does not generate an acknowledge at the appropriate time during a host smbus cycle. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2h bit[hcyc_en]. rwc 1col_sts0 collision status. host collision status. this bit is set by the hardware when a host transfer is initiated while the smbus is busy. this bit is cleared when a 1 is written to it; writing a 0 to this bit has no effect. this bit will generate an smi or sci interrupt if enabled to do so by pm00 +e2h bit[hcyc_en]. rwc
266 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information bits[9:8] are powered by the vdd_soft plane and reset by rst_soft rather than pwrgd. 0abrt_sts0 abort status. host transfer abort status. this bit is set by the hardware after a host transfer is aborted by pm00 +e2h bit[abort] command. this bit generates an smi or sci interrupt if enabled to do so by pm00 +e2h bit[hcyc_en]. rwc sm bus global status (continued) pm00 + offset e1h ? e0h bit name default description access type sm bus global enable register pm00 + offset e3h ? e2h bit name default description access type 15-11 0 reserved. these bits must remain 0 for proper operation. rw 10 snba_en 0 sm bus alert enable. 1 = specifies that an smi or sci interrupt will be generated when the smbalert# pin is asserted. when low, no interrupts are generated when this pin is set. this bit has no effect unless the smbalert# function is selected by function 3, offset 46, bits[10:9]. rw 9 hslv_en 0 host-as-slave address match enable. host-as-slave address match interrupt enable. 0 = (disabled) no interrupts are generated when pm00 +e0h [hslv_sts] is set. 1 = (enabled) specifies that an smi or sci interrupt will be generated when that bit is set. rw 8snp_en0 snoop address match enable. 0 = (disabled) no interrupts are generated when this bit is set. 1 = (enabled) specifies that an smi or sci interrupt will be generated when pm00 +e0h bit[snp_sts] is set high. rw 7-6 0 reserved. these bits must remain 0 for proper operation. rw 5abort 0 abort current host command. when this bit is set by software, the smbus logic generates a stop event on the smbus pins as soon as possible (this may take a while if the smbus slave has been instructed to generate zeros during a read cycle). after the stop event is generated, pm00 +e0h bit[abrt_sts] is set. wo 4hcyc_en0 host cycle interrupt enable . 0 = (disabled) no interrupts are generated when these bits are set. 1 = (enabled) the smbus host controller status bits, pm00 +e0 bits [to_sts, hcyc_sts, prerr_sts, col_sts, abrt_sts], are enabled to generate smi or sci interrupts. rwc 3host_stc0 host start command. when this bit is set by software, the smbus host logic initiates the smbus cycle specified by cyctype. writes to this field are ignored while pm00 +e0h bit[hst_bsy] is active. wo 2-0 cyc_type 000 cycle type. host-generated smbus cycle type. this field specifies the type of smbus cycle that is generated when it is initiated by the hostst command. this field is decoded as shown in table 81 below. rw
chapter 7 registers 267 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information writes to the cycle type field are ignored while pm00 +e0h bit[hst_bsy] is active. table 81. sm bus cycle type encoding cycle type sm bus cycle type registers (for each of these, the slave address is specified by pm00 +e4h bits[7:1] and receive or read versus send or write is specified by pm00 +e4 bit[0]) 000 quick command data bit in pm00 +e4h bit[0] 001 receive or send byte data in pm00 +e6h bits[7:0]. if the address in pm00 +e4h is ? b0001_1001 and data received is ? b111_0xxx, then another byte will be received in pm00 +e6h bits[15:8]; see the smbalert description in the system management section of this document. 010 read or write byte command in pm00 +e8h; data in pm00 +e6h bits[7:0] 011 read or write word command in pm00 +e8h; data in pm00 +e6h bits[15:0] 100 process call command in pm00 +e8h; write data is placed in pm00 +e6h bits[15:0]; then this data is replaced with the read data in the second half of the command 101 read or write block command in pm00 +e8h; count data in pm00 +e6h bits[5:0]; block data in the pm00 +e9h fifo 11x reserved sm bus host address register pm00 + offset e5h ? e4h bit name default description access type 15-8 hst10ba 00000000 host 10 bit address lsbs . these bits store the second byte of the address, used in 10-bit smbus host-as-master transfers. if hstaddr == ? b1111_0xx, then the cycle is specified to use 10-bit addressing. if hstaddr is any other value, then hst10ba is not utilized. hst10ba are the upper 8 bits and the least significant 2 bits come from the hstaddr field. rw 7-1 hstaddr 0000000 host cycle address. these bits specify the 7-bit address to the smbus generated by the host (as a master) during smbus cycles that are initiated by pm00 +e2 bit[hostst]. rw 0rc 0 read cycle. 0 = specifies that the cycle generated by a write to pm00 +e2 bit[hostst] is a write cycle or send command. 1 = specifies that the cycle generated by a write to pm00 +e2 bit[hostst] is a read cycle or receive command. rw
268 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information the register above is powered by the vdd_soft plane and reset by rst_soft rather than pwrgd. sm bus host data register pm00 + offset e7h ? e6h bit name default description access type 15-0 hstdata 00000000 00000000 host data). this register is written to by software to specify the data to be passed to the smbus during write and send cycles. it is read by software to specify the data passed to host controller by the smbus during read and receive cycles. bit[0] specifies the data written or read during the quick command cycle. bits[7:0] specify the data for byte read and write cycles, send byte cycles, and receive byte cycles. bits[15:0] are used for word read and write cycles and process calls. bits[5:0] are used to specify the count for block read and write cycles. rw sm bus host command field register pm00 + offset e8h bit name default description access type 7-0 host command 00000000 host command. this specifies the command field passed to the smbus by the host controller during read byte, write byte, read word, write word, process call, block read, and block write cycles. host cycles are initiated by pm00 + e2h bit[hostst]. wo sm bus host block data fifo access port pm00 + offset e9h bit name default description access type 7-0 host command 00000000 host data fifo. for block write commands, software loads 1 to 32 bytes into this port before sending them to the smbus via the pm00 + e2h bit[hostst] command. for block read commands, software read 1 to 32 bytes from this port after the block read cycle is complete. if, during a block read or write, an error occurs, then the fifo is flushed by the hardware. read and write accesses to this port while the host is busy (pm00 +e0h bit[hst_bsy]) are ignored. rw sm bus host as slave data register pm00 + offset ebh ? eah bit name default description access type 15-0 hslvdata 00000000 00000000 host-as-slave-data. when the smbus logic determines that the current smbus cycle is directed to the host ? s slave logic (because the address matches pm00 + eeh), then the data transmitted to the AMD-756 during the cycle is latched in this register. also, if the address matches the snoop address in pm00 + efh, then the cycle is assumed to be a write word and the data is stored in this register. ro
chapter 7 registers 269 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information the register above is powered by the vdd_soft plane and reset by rst_soft rather than pwrgd. the register above is powered by the vdd_soft plane and reset by rst_soft rather than pwrgd. the register above is powered by the vdd_soft plane and reset by rst_soft rather than pwrgd. sm bus host-as-slave device address register pm00 + offset edh ? ech bit name default description 0-state 15-8 hslv10da 00000000 host-as-slave 10 bit address lsbs. these bits store the second byte of the address, used in 10-bit smbus host-as-master transfers. if hstaddr == ? b1111_0xx, then the cycle is specified to use 10-bit addressing. if hstaddr is any other value, then hst10ba is not utilized. hst10ba are the upper 8 bits and the least significant 2 bits come from the hstaddr field. ro 7-1 hslvda 0000000 host-as-slave device address. this field stores the second byte of the device address used in 10-bit smbus transfers to the host as a slave. if hslvda == ? b1111_0xx, then the cycle is specified by the smbus specification to transmit a 10-bit device address to the host-as-slave logic and the second byte of that device address is stored in this field. if hslvda is any other value, then hslv10ba is ignored. ro 0snpl 0 snoop command lsb. if the smbus cycle address matches pm00+efh, then the cycle is assumed to be a write word. the lsb of the command field for the cycle is placed in this bit (and the other 7 bits are placed in hslvda). ro sm bus host-as-slave host address register pm00 + offset eeh bit name default description access type 7-1 hslvddr 0001000 host-as-slave address. the smbus logic compares the address generated by masters over the smbus to this field to determine if there is a match (also, for a match to occur, the read-write bit is required to specify a write command). if a match occurs, then the cycle is assumed to be a write word command to the host, with the slave ? s device address transmitted during the normal command phase. the device address is captured in pm00+ech and the data is capture in pm00+eah for the cycle. after the cycle is complete, pm00+e0h bit[hslv_sts] is set. rw 00 reserved. this bit must remain 0 for proper operation. rw sm bus snoop address register pm00 + offset efh bit name default description access type 7-1 snpaddr 0001000 snoop address. the smbus logic compares the address generated by masters over the smbus to this field to determine if there is a match (regardless as to whether it is a read or a write). if there is a match, then pm00+e0h bit[snp_sts] is set high after the cycle completes. if the address specified here matches pm00+eeh, then pm00+e0h bit[snp_sts] will not be set high. rw 00 reserved. this bit must remain 0 for proper operation. rw
270 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.8 function 4 registers (usb) this section describes the universal serial bus (usb) control registers of the AMD-756 peripheral bus controller. this controller is compatible with the usb specifications. 7.8.1 function 4 usb configuration vendor id function 4 offset 01h ? 00h bit name default description access type 15-0 vendor id 00010000 00100010 vendor id = 1022h ro device id function 4 offset 03h ? 02h bit name default description access type 15-0 device id 01110100 00000100 device id = 740ch ro command register function 4 offset 05h ? 04h bit name default description access type 15-10 000000 reserved. always reads zero. 9b2b 0 fast back-to-back enable. input port value always 0 8 serr 0 serr# response. serr# is asserted when it detects an address parity error. 0 = serr# disabled 1 = serr# enabled rw 7wcc 0 wait cycle control. the AMD-756 controller does not insert a wait state between the address and data on the ad lines. always 0 6perr 0 parity error response. the AMD-756 does not have a perr# pin. always 0 5vga 0 vga palette snooping. always reads 0. always 0 4mwi 0 memory write invalidate command. the memory write and invalidate command will only occur if the cache line size is set to 32 bytes and the memory write is exactly one cache line. 0 = disabled 1 = enable memory write and invalidate commands rw 3scm 0 special cycle monitoring. always reads 0. disabled 2bm 0 bus master. 0 = disabled 1 = enabled rw 1mem 0 memory space. 0 = disabled 1 = enables the ability to access the memory mapped space of the specified ide controller. rw 0i/o 0 i/o space. 0 = the device does not respond to any i/o addresses for either compatible or native mode. 1 = enabled to respond to i/o addresses rw
chapter 7 registers 271 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information status function 4 offset 07h ? 06h bit name default description access type 15 dpe 0 parity error detected. always reads 0. r 14 serr 0 serr error. always reads 0. r 13 ria 0 received initiator abort. this bit is set by the usbc initiator when its transaction is terminated with initiator abort. 0 = pci transactions proceeding normally. 1 = the amd-751 system controller has detected that a transaction was terminated before completion. rwc 12 rta 0 received target abort (rwc). the usbc receives a target abort. this bit is set by simultaneously deasserting devsel# and asserting stop#. 0 = no abort received 1 = transaction aborted by target 11 sta 0 signaled target abort. always reads 0. the usbc signals target abort. 0 = no abort received 1 = transaction aborted by usbc no abort signaled 10-9 devsel# timing 01 devsel# timing (always reads 01). this field indicates that the slowest devsel# timing is medium. the AMD-756 peripheral bus controller only implements the medium timing. always reads 01 8ppe 0 pci parity error detected. always reads 0. the AMD-756 peripheral bus controller does not have a perr# pin. always reads 0 7fbbc 0 fast back-to-back capability. the AMD-756 peripheral bus controller can accept fast back-to-back transactions from the different agents. always reads 1 6-0 0 reserved. always reads 0. revision id function 4 offset 08h bit name default description access type 7-0 silicon revision code 00000101 the current silicon revision code is 05h = revision a. ro programming interface function 4 offset 09h bit name default description access type 7-0 00010000 this register defines the programming interface used as open hci. bits devsel# speed 00 fast 01 medium 10 slow 11 reser ved
272 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information sub class code function 4 offset 0ah bit name default description access type 7-0 0000011 this register defines the sub class used as usb. base class code function 4 offset 0bh bit name default description access type 7-0 00001100 the base class code 0ch indicates a serial bus controller. cache line size function 4 offset 0ch bit name default description access type 7-0 00001000 this register identifies the system cache line size in units of 32-bit words. the usbc will only store the value of bit 3 in this register since the cache line size of 32 bytes is the only value applicable to the design. any value other than 08h written to this register will be read back as 00h. r/w latency timer function 4 offset 0dh bit name default description access type 7-0 00010000 latency timer. this register identifies the value of the latency timer in pci clocks. r header type function 4 offset 0eh bit name default description access type 7-0 00000000 this register contains the value 00h. ro bist function 4 offset 0fh bit name default description access type 7-0 00000000 this register contains the value 00h. the usbc dos not implement built in self test. ro base address register 0 function 4 offset 13h ? 10h bit name default description access type 31-12 base address high 0 base address high. this field is loaded by bios software to determine the base address a[30:11] of the memory-mapped usb-ohci registers. rw 11-4 base address low 0 base address low. this field is cleared to indicate that 4 kbytes is allocated to usb memory-mapped control registers and that the registers reside at a 4-kbyte boundary per pci specification 2.1. always reads 0 3pre 1 prefetchable. this bit indicates that this range can not be prefetched. note: discrepancy between definition and figure for value of bit. always reads 0 2-1 type 00 type. these bits are cleared to indicate that bar0 is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. always read 0
chapter 7 registers 273 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information this register is used by the usb driver software to set the memory location of the ohci memory-mapped control registers. 0mem 0 memory. this bit is cleared to indicate that bar0 maps into memory space. always reads 0 base address register 0 (continued) function 4 offset 13h ? 10h bit name default description access type interrupt line register function 4 offset 3ch bit name default description access type 7-0 00000000 this register contains the default value 00h. it identifies which of the system interrupt controllers the devices interrupt pin is connected to. the value of this register is used by device drivers and has no direct meaning to usbc. ro interrupt pin register function 4 offset 3dh bit name default description access type 7-0 00000100 this register identifies which interrupt pin a device uses. since usbc uses intd#, this value is set to 04h. ro min grant register function 4 offset 3eh bit name default description access type 7-0 00000000 this register contains the value 00h. it specifies the desired settings for how long a burst usbc needs assuming a clock rate of 33 mhz. the value specifies a period of time in units of 1/4 microsecond. ro max latency register function 4 offset 3fh bit name default description access type 7-0 00000000 this register contains the value 00h. it specifies the desired settings for how often usbc needs access to the pci bus assuming a clock rate of 33 mhz. the value specifies a period of time in units of 1/4 microsecond. ro operational mode register function 4 offset 44h bit name default description 0-state 7-1 000000 reserved. this register selects which operational mode is enabled. bits defined as write-only are read as 0 ? s. wo 0db16 0 data buffer region 16 (rw). 0 = 323-byte data buffer. 1 = 16-byte data buffer. this bit is set when overcurrentindicator changes. rw
274 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.8.2 usb memory mapped registers (open hci registers) these memory mapped registers are relative to function 4 offset 10 (bar0). hcrevision bar0 + offset 01h ? 00h bit name default description access type 15-9 0 reserved. always read 0. ro 8leg 1 legacy . always reads 1. indicates that the legacy support registers are present in usb controller. ro 7-4 major revision 0001 major revision. indicates the openhci specification major revision number implemented. ro 3-0 minor revision 0000 minor revision. indicates the openhci specification minor revision number implemented. ro hccontrol bar0 + offset 05h ? 04h bit name default description access type 15-11 0 reserved. always read 0. 10 rwe 0 remote wakeup enable. always reads 1. indicates that remote wakeup is always enabled. note: discrepancy between default definitions in old figure and in text. ro 9rw 1 remote wakeup connected . always reads 1. indicates that the usbc supports a remote wakeup signal. ro 8ir 0 interrupt routing. 0 = interrupts routed to normal interrupt mechanism (int) 1 = interrupts routed to smi rw 7-6 state 00 host controller functional state . sets the host controller state: the host controller may force a state change from usbsuspend to usbresume after detecting resume signaling from a downstream port. rw 5ble 0 bulk list enable. 0 = bulk list processing disabled 1 = bulk list processing enabled rw bits host controller state 00 usb reset 01 usb resume 10 usb operational 11 usb suspend
chapter 7 registers 275 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 4cle 0 control list enable. 0 = control list processing disabled 1 = control list processing enabled rw 3ie 0 isochronous enable. 0 = disables the isochronous list when the periodic list is enabled (so interrupt eds may be serviced). while processing the periodic list, the host controller will check this bit when it finds an isochronous endpoint descriptor (ed). 1 = enables the isochronous list. rw 2ple 0 periodic list enable. this bit enables processing of the periodic (interrupt and isochronous) list. the host controller checks this bit prior to attempting any periodic transfers in a frame. 0 = disabled 1 = enabled rw 1-0 cbsr 00 control bulk service ratio (rw). specifies the number of control endpoints serviced for every bulk endpoint. encoding is n+1 where n is the number of control endpoints. rw hccommand bar0 + offset 08h bit name default description 0-state 7-4 0 reserved. always reads 0. 3ocr 0 ownership change request. 1 = sets the ownershipchange field in hcinterruptstatus register. the bit is cleared by software. rw 2blf 0 bulk list filled. 0 =begin processing the head of the bulk list. cleared by the host controller each time it begins processing the head of the bulk list. 1 = indicates there is an active ed on the bulk list. the bit may be set by either software or the host controller. rw 1clf 0 control list filled. 0 = begin processing the head of the control list. the bit is cleared by the host controller each time it begins processing the head of the control list. 1= indicates there is an active ed on the control list. the bit may be set by either software or the host controller. rw 0hcr 0 host controller reset (rw). 0 = no reset, cleared by the host controller upon completion of the reset operation. 1 = start a reset operation. rw hccontrol (continued) bar0 + offset 05h ? 04h bit name default description access type bits number of control endpoints 00 1 01 2 10 3 11 4
276 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information hcstatus bar0 + offset 0ah bit name default description access type 7-2 000000 reserved. always reads 0. 1-0 00 schedule overrun count. this field increments every time the schedulingoverrun bit in hcinterruptstatus register is set. the count wraps from ? 11 ? to ? 00 ? . rw hcinterrupt status bar0 + offset 0dh ? 0ch bit name default description access type 1-state 15-7 0 reserved. must remain 0 for proper operation. rw 6rhs 0 root hub status change. this bit is set when the content of hcrhstatus or the content of any hcrhportstatus register has changed. ro 5fno 0 frame number overflow. this bit is set when bit 15 of framenumber changes value from ? 0 ? to ? 1 ? or from ? 1 ? to ? 0 ? . rw 4err 0 unrecoverable error. (always reads 0. not implemented. 3rd 0 resume detected. this bit is set when the host controller detects resume signaling on a downstream port. 0 = resume not detected 1 = resume detected rw 2sof 0 start of frame. this bit is set when the frame management block signals a ? start of frame ? event. rw 1wbdh 0 writeback done head. this bit is set after the host controller has written hcdonehead to hccadonehead. rw 0so 0 scheduling overrun. 0 = no overrun 1 = list processor determines a schedule overrun has occurred rw bits schedule overrun count 00 0 01 1 10 2l 11 3
chapter 7 registers 277 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information hcownership status bar0 + offset 0fh ? 0eh bit name default description access type 15 0 reserved. must remain 0 for proper operation. rw 14 0 ownership change. this bit is set when the ownershipchangerequest bit of hccommandstatus is set. ro 13-0 0 reserved. must remain 0 for proper operation. rw hcinterrupt enable bar0 + offset 11h ? 10h bit name default description access type 15-7 0 reserved. must remain 0 for proper operation. rw 6rhse 0 root hub status change enable. 0 = ignore 1 = enable interrupt generation rw 5fnoe 0 frame number overflow enable. 0 = ignore 1 = enable interrupt generation rw 4erre 0 unrecoverable error. always reads 0. not implemented. 3rde 0 resume detected enable. 0 = ignore 1 = enable interrupt generation rw 2sofe 0 start of frame enable. 0 = ignore 1 = enable interrupt generation rw 1wbde 0 writeback done head enable. 0 = ignore 1 = enable interrupt generation rw 0soe 0 scheduling overrun enable. 0 = ignore 1 = enable interrupt generation rw hcownership enable bar0 + offset 13h ? 12h bit name default description access type 15 mie 0 master interrupt enable. 0 = ignore 1 = enable interrupt generation rw 14 oc e 0 ownership change enable. 0 = ignore 1 = enable interrupt generation ro 13-0 0 reserved. must remain 0 for proper operation. rw hcinterrupt disable bar0 + offset 15h ? 14h bit name default description access type 15-7 0 6rhsd 0 root hub status change disable. 0 = ignore 1 = disable interrupt generation rw 5fnod 0 frame number overflow disable. 0 = ignore 1 = disable interrupt generation rw 4errd 0 unrecoverable error. always reads 0. not implemented. 3rdd 0 resume detected disable. 0 = ignore 1 = disable interrupt generation rw 2sofd 0 start of frame disable. 0 = ignore 1 = disable interrupt generation rw 1wbdd 0 writeback done head disable. 0 = ignore 1 = disable interrupt generation rw 0sod 0 scheduling overrun disable. 0 = ignore 1 = disable interrupt generation rw
278 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information hcownership disable bar0 + offset 17h ? 16h bit name default description access type 15 mid 0 master interrupt disable. 0 = ignore 1 = disable interrupt generation rw 14 ocd 0 ownership change disable. 0 = ignore 1 = disable interrupt generation ro 13-0 0 reserved. must remain 0 for proper operation. rw hchcca bar0 + offset 1bh ? 18h bit name default description access type 31-8 hcca 0 pointer to hcca base address . rw 7-0 0 reserved. must remain 0 for proper operation. rw hcperiod current ed bar0 + offset 1fh ? 1ch bit name default description access type 31-4 hcca 0 period current ed. pointer to the current periodic list ed. rw 3-0 0 reserved. must remain 0 for proper operation. rw hccontrol head ed bar0 + offset 23h ? 20h bit name default description access type 31-4 cha 0 control head address. pointer to the control list head ed. rw 3-0 0 reserved. must remain 0 for proper operation. rw hccontrol current ed bar0 + offset 27h ? 24h bit name default description access type 31-4 hcc 0 current control ed. pointer to the current control list ed. rw 3-0 0 reserved. must remain 0 for proper operation. rw hcbulk head ed bar0 + offset 2bh ? 28h bit name default description access type 31-4 blh 0 bulk list head ed. pointer to the bulk list head ed. ro 3-0 0 reserved. must remain 0 for proper operation. rw hcbulk current ed bar0 + offset 2fh ? 2ch bit name default description access type 31-4 bcl 0 bulk current list ed. pointer to the current bulk list ed. ro 3-0 0 reserved. must remain 0 for proper operation. rw
chapter 7 registers 279 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information hcdone head ed bar0 + offset 33h ? 30h bit name default description access type 31-4 dlh 0 done list head ed. pointer to the done list head ed. ro 3-0 0 reserved. must remain 0 for proper operation. rw hcframe interval bar0 + offset 37h ? 34h bit name default description access type 31 fi 0 frame interval toggle. this bit is toggled by hcd whenever it loads a new value into the frame interval field. 30-16 fs largest data packet 0 fs largest data packet. must remain 0 for proper operation. rw 15-14 0 reserved. must remain 0 for proper operation. rw 13-0 frame interval 10111011 011111 frame interval. this field specifies the length of a frame as (bit times - 1). for 12,000 bit times in a frame, a value of 11,999 is stored here. rw hcframe remaining bar0 + offset 3bh ? 38h bit name default description access type 31 fr 0 frame remaining toggle. this bit is toggled by hcd whenever it loads a new value into the frame remaining field. rw 30-14 0 reserved. must remain 0 for proper operation. rw 13-0 frame remaining 0 bits 13 ? 0frame remaining (rw). this field is a 14 bit decrementing counter used to time a frame. when the host controller is in the usboperational state the counter decrements each 12 mhz clock period. when the count reaches 0, the end of a frame has been reached. the counter reloads with frameinterval at that time. in addition, the counter loads when the host controller transitions into the usboperational state. rw hcframe number bar0 + offset 3fh ? 3ch bit name default description 0-state 31-16 0 reserved. must remain 0 for proper operation. rw 15-0 frame number 0 frame number. this field is a 16 bit incrementing counter. the count is incremented coincident with the loading of frameremaining. the count will roll over from ? ffffh ? to ? 0h. ? writing to this register while the usb controller is operational will have unexpected results. rw hcperiodic start bar0 + offset 43h ? 40h bit name default description access type 31-14 0 reserved. must remain 0 for proper operation. rw 13-0 periodic start 0 periodic start. this field contains a value used by the list processor to determine where in a frame the periodic list processing must begin. rw
280 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information hcls threshold bar0 + offset 47h ? 44h bit name default description access type 31-12 0 reserved. must remain 0 for proper operation. rw 11-0 lst 0 low speed threshold. this field contains a value used by the frame management block to determine whether or not a low speed transaction can be started in the current frame. rw hcrh descriptor a1 bar0 + offset 49h ? 48h bit name default description access type 15-13 0 reserved. must remain 0 for proper operation. rw 12 nocp 0 no over-current protection mode. 0 = over-current status is reported 1 = over-current status is not reported this bit should be set to support the external system port over current implementa- tion. rw 11 ocp 0 over-current protection mode. 0 = global over-current protection 1 = individual over-current protection this bit is valid only when no over-current protection is cleared. rw 10 dt 0 device type. 0 = not a compound device 1 = compound device ro 9nps 0 no power switching. 0 = ports are power switched 1 = ports are always on this bit should be set to support external system port power switching. rw 8psm 0 power switching mode. 0 = global switching 1 = individual switching this bit is valid only when no power switching is cleared. rw 7-0 number of down stream ports 00000100 number of down stream ports. 4 ports are supported. ro hcrh descriptor a2 bar0 + offset 4bh ? 4ah bit name default description access type 15-10 0 reserved. always read 0. 9-8 power good time 01 power good time . power switching is effective within 2 ms. the field value is the number of 2 ms intervals. only bits [9:8] are implemented as r/w. the remaining bits are read only as ? 0 ? . it is not expected that these bits be written to anything other than 1h, but limited adjustment is provided. this field should always be written to a non-zero value. rw 7-0 0 reserved. must remain 0 for proper operation. rw bits power good time 00 0 milliseconds 01 2 milliseconds (default) 10 4 milliseconds 11 6 milliseconds
chapter 7 registers 281 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information hcrh descriptor b bar0 + offset 4fh ? 4ch bit name default description access type 31-16 power control mask 0 power control mask. nopowerswitching is cleared and powerswitchingmode is set (individual port switching). 0 =the port only responds to global power switching commands (set/clearglobalpower). 1 = the port only responds to individual port power switching commands (set/clearportpower). bit 16 corresponds to port zero and is reserved. bit 17 corresponds to port 1, bit 18 to port 2, etc. unimplemented ports are reserved, read/write ? 0 ? . rw 15-0 device removable 0 bits 15 ? 0device removable. 0 = device removable 1 = device not removable bit 0 corresponds to port zero and is reserved. bit 1 corresponds to port 1, bit 2 to port 2, etc. unimplemented ports are reserved, read/write ? 0 ? . rw hcrh status a bar0 + offset 51h ? 50h bit name default description access type 15 rwe 0 remote wakeup enable. 0 = disabled 1 = enables ports ? connectstatuschange as a remote wakeup event. and also reports remote wake up status. writing a ? 0 ? has no effect. this function is disabled by writing offset 52 bit 15. rw 14-2 0 reserved. always read 0. 1oci 0 over current indicator. this bit reflects the state of the ovrcur pin. 0 = no over-current condition 1 = over-current condition this field is only valid if noovercurrentprotection and overcurrentprotectionmode are cleared. ro 0lps 0 local power status . always reads 0. not supported. (read) always reads ? 0 ? . (write) clearglobalpower writing a ? 1 ? issues a clearglobalpower command to the ports. writing a ? 0 ? has no effect. hcrh status b bar0 + offset 53h ? 52h bit name default description access type 15 crw 0 clear remote wakeup. this bit disables ports ? connectstatuschange as a remote wakeup event. 0, 1 = no effect status is reported in offset 50 bit 15. wo 14-2 0 reserved. always read 0.
282 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 1ocic 0 over current indicator change. 0 = no change 1 = overcurrentindicator changes. this field is only valid if noovercurrentprotection and overcurrentprotectionmode are cleared. ro 0lpsc 0 local power status change (always reads 0). not supported. (read) always reads ? 0 ? . (write) setglobalpower writing a ? 1 ? issues a setglobalpower command to the ports. writing a ? 0 ? has no effect. hcrh port 1 status bar0 + offset 57h ? 54h bit name default description access type 31-21 0 reserved. these bits must remain 0 for proper operation. rw 20 prsc 0 port reset status change. 0 = port reset is not complete. 1 = port reset signal is complete. rwc 19 pocc 0 port over current indicator change. 0 = no change. 1 = overcurrentindicator changed. rwc 18 p ssc 0 port suspend status change. 0 = port has not resumed. 1 = the selective resume sequence for the port is completed. rwc 17 pesc 0 port enable status change. 0 = port has not been disabled. 1 = the port has been disabled due to a hardware event (cleared portenablestatus). rwc 16 ccsc 0 connection change status. 0 = no connect or disconnect event detected. 1 = indicates hardware detection of a connect or disconnect event. if deviceremoveable is set, this bit is set to ? 1 ? . rw 15-10 0 reserved. always read 0. 9lsd 0 low speed device attached . this bit defines the speed of the attached device. it is only valid when currentconnectstatus is set. 0 = full speed device 1 = low speed device rw 8pps 0 port power status. this bit reflects the power state of the port regardless of the power switching mode. 0 = port power is off. 1 = port power is on. if nopowerswitching is set, this bit is always read as ? 1 ? . rwc 7-5 0 reserved. these bits must remain 0 for proper operation. rw 4prs 0 port reset status . 0 = port reset signal is not active 1 = port reset active writing a ? 1 ? to the setportreset bit sets portresetstatus. writing a ? 0 ? has no effect. rwc hcrh status b (continued) bar0 + offset 53h ? 52h bit name default description access type
chapter 7 registers 283 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information hcrh port 2 status bar0 + offset 5bh ? 58h hcrh port 3 status bar0 + offset 5fh ? 5ch hcrh port 4 status bar0 + offset 63h ? 60h these registers have the same bit definitions as the above. 3poci 0 port over current indicator. portovercurrentindicator supports global over-current reporting. this bit reflects the state of the ovrcur pin dedicated to this port. this field is only valid if noovercurrentprotection is cleared and overcurrentprotectionmode is set. 0 = no over-current condition 1 = over-current condition writing a ? 1 ? to the clearportsuspend bit initiates the selective resume sequence for the port. writing a ? 0 ? has no effect. rwc 2pss 0 port suspend status. this bit is set when the port is selectively suspended. 0 = port is not suspended. 1 = port is selectively suspended. writing a ? 1 ? to the setportsuspend bit sets portsuspendstatus. writing a ? 0 ? has no effect. rwc 1pes 0 port enable status. 0 = port disabled 1= port enabled writing a ? 1 ? to the setportenable bit sets portenablestatus. writing a ? 0 ? has no effect. rwc 0 ccs 0 current connection status. 0 = no device connected 1 = device connected (read) if deviceremoveable is set (not removable) this bit is always ? 1 ? . (write) writing a ? 1 ? to the clearportenable bit clears portenablestatus. writing a ? 0 ? has no effect. rwc hcrh port 1 status (continued) bar0 + offset 57h ? 54h bit name default description access type hcenable and control bar0 + offset 101h ? 100h bit name default description access type 15-9 0 reserved. always read 0. 8a20s 1 a20 state. indicates current state of gate a20 on keyboard controller. used to compare against value written to 60h when gatea20sequence is active. 0 = a20 inactive 1 = a20 active rw 7irq12 0 irq12 active. 0 = no transition 1 = indicates that a positive transition on irq12 from keyboard controller has occurred. software can write a 1 to this bit to clear it to 0 sw write of a 0 has no effect. rwc
284 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 6irq1 0 irq1 active. 0 = no transition 1 = indicates that a positive transition on irq1 from keyboard controller has occurred. software can write a 1 to this bit to clear it to 0 sw write of a 0 has no effect. rwc 5ga20s 0 gate a20 sequence. 0 = indicates a data value other than d1h was written to i/o port 64h 1 = indicates a data value of d1h was written to i/o port 64h ro 4eirqe 0 external irq enable. 0 = disabled 1 = enabled irq1 and irq12 from the keyboard controller cause an emulation interrupt. the function controlled by this bit is independent of the setting of the emulationenable bit in this register. rw 3irqe 0 irq enable. the usbc will generate irq1 or irq12 as long as the outputfull bit in hcestatus is set to 1. if the auxoutputfull bit of hcestatus is 0 then irq1 is generated and if it is 1, then an irq12 is generated. see table 82 below for details. 0 = irq1 1 = irq12 rw 2cp 0 character pending. 0 = disabled 1 = an emulation interrupt is generated when the outputfull bit of the hc enableandstatus register is cleared. rw 1ei 0 emulation interrupt. this bit is a static decode of the emulation interrupt condition. 0 = no interrupt 1 = interrupt ro 0ee 0 emulation enable. 0 = disabled 1 = the usbc is enabled for legacy emulation. the usbc will decode accesses to i/o registers 60h and 64h and generate irq1 and/or irq12. these interrupts invoke the emulation software. rw hcenable and control (continued) bar0 + offset 101h ? 100h bit name default description access type table 82. bit relations irq enable outputfull in hcestatus auxoutputfull in hcestatus character pending in hcecontrol action 0 x x x none 1 0 x 1 emulation interrupt 11 0 xirq1 11 1 xirq12
chapter 7 registers 285 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information hceinput bar0 + offset 107h ? 104h bit name default description access type 31-8 0 reserved. always reads 0. 7-0 data in x data in. this register captures data that is written to port 60h and 64h. rw hceoutput bar0 + offset 10bh ? 108h bit name default description access type 31-8 0 reserved. always reads 0. 7-0 data out xx0xxxxx data out. this register holds data that is returned when an i/o read of port 60h is performed by application software. rw hc-control and status bar0 + offset 10ch bit name default description 0-state 1-state 7par 0 parity. 0 = no parity error 1 = parity error on keyboard/mouse data rw 6t 0 timeout. 0 = no timeout 1 = timeout occurred rw timeout occurred 5aof 0 aux output full. irq12 is asserted whenever this bit, the outputfull, and the irqen bit s are set. 0 = auxiliary output not full 1 = auxiliary output full rw aux output full 4is 0 inhibit switch. this bit reflects the state of the keyboard inhibit switch. 0 = inhibited 1 = not inhibited rw not inhibited 3cd 0 command data. 0 = indicates an i/o write to port 60h 1 = indicates an i/o write to port 64h ro 2 flag 0 flag. this bit is used as a system flag by software to indicate a warm or cold boot. 0 = cold boot 1 = warm boot rw warm boot 1if 0 input full . 0 = no i/o write 1 = except for the case of a gate a20 sequence, one indicates an i/o write to address 60h or 64h. while this bit is set to 1 and emulation is enabled, an emulation interrupt condition exists. (see gate a20 sequence in ch5 for a detailed description.) rw 0of 0 output full . the usbc will clear this bit on a read of i/o port 60h. if irqen is set and auxoutputfull is cleared then an irq1 is generated as long as this bit is set. if irqen is set and auxoutputfull is set then irq12 will be generated as long as this bit is set. while this bit is 0 and characterpending in hcecontrol is set, an emulation interrupt condition exists. 0 = indicates a read of i/o port 60h. 1 = generate irq12 if irqen is set and auxoutputfull is cleared. rw
286 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 7.8.3 i/o apic registers memory mapped registers the i/o apic registers are accessed by using the two 32-bit registers ? ioregsel and iowin. these registers are located at fixed memory addresses fec0_0000h and fec0_0010h. to access any one of the ioapic registers listed in the table, the io regsel register is written with the address of the apic register. the iowin register is then used to read or write the data from the ioapic register addressed by the ioregsel register. all ioapic registers are accessed by 32-bit loads and stores. bits 31 ? 8 reserved (always read 0) bits 7-0 apic register address ? this field contains the index to ioapic registers to be accessed via the iowin register. bits 31 ? 0 apic register data ? this register contains the read/write data from the ioapic register addressed in the ioregsel register. ioregsel fec0_0000h 313029282726252423 222120191817161514131211109876543210 reserved apic register address reset00000000000000000000000000000000 iowi n fec0_0010h 313029282726252423 222120191817161514131211109876543210 apic register data reset000000000000000000000000 xxxxxxxx
chapter 7 registers 287 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information apic id-i/o apic identification register this register contains the 4-bit apic id. the id serves as a physical name of the ioapic. all apic devices using the apic bus should have a unique apic id. the apic bus arbitration id for the i/o unit is also written during a write to the apicid register (same data is loaded into both). this register must be programmed with the correct id value before using the ioapic for message transmission. bits 31 ? 8 reserved (always read 0) bits 27 ? 24 ioapic id (rw) ? this field contains the ioapic identification. bits 23 ? 0 reserved (always read 0) apic id-i/o apic version register the ioapic version register identifies the apic hardware version. software can use this to provide compatibility between different apic implementations and their versions. in addition, this register provides the maximum number of entries in the i/o redirection table. bits 31 ? 24 reserved (always read 0) bits 23 ? 16 max redirection entries ? this field contains the entry number (0 being the lowest entry) of the highest entry in the i/o redirection table. the value is equal to the number of interrupt input pins for the ioapic minus one. the range of values is 0 through 239. for this ioapic, the value is 17h. bits 15 ? 8 reserved (always read 0) bits 7 ? 0 apic version (ro) ? this 8-bit field identifies the implementation version. the version number assigned to the ioapic is 11h. ioapic identification index 00h 313029282726252423 222120191817161514131211109876543210 reset reserved id reserved 0000000000000 0000000000 xxxxxxxx ioapic version index 01h 313029282726252423 222120191817161514131211109876543210 reset reserved max rdir entries reserved apic version 00000000000101110000000000010001
288 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information apicarb register the apicarb register contains the bus arbitration priority for the ioapic. this register is loaded when the ioapic id register is written. the apic uses a one wire arbitration to win bus ownership. a rotating priority scheme is used for arbitration. the winner of the arbitration becomes the lowest priority agent and assumes an arbitration id of 0. all other agents, except the agent whose arbitration id is 15, increment their arbitration ids by one. the agent whose id was 15 takes the winner ? s arbitration id and increments it by one. arbitration ids are changed (incremented or assumed) only for messages that are transmitted successfully. (except in the case of low-priority messages where arbitration id is changed even if the message was not successfully transmitted.) a message is transmitted successfully if no checksum error or acceptance error is reported for that message. the apicarb register is always loaded with ioapic id during a level-triggered init with de-assert message. bits 31 ? 28 reserved (always read 0) bits 27 ? 24 ioapic arb_id (rw) ? this field contains the ioapic arbitration id. bits 23 ? 0 reserved (always read 0) ioapic arbitration index 02h 313029282726252423 222120191817161514131211109876543210 reset reserved arb_id reserved 00000000000000000000000000000000
chapter 7 registers 289 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information redirection table entry registers there are 48 i/o redirection table entry registers ? located in doubleword pairs at even and odd index numbers. each register is a dedicated entry for each interrupt input signal. unlike irq pins of the 8259a, the notion of interrupt priority is completely unrelated to the position of the physical interrupt input signal on the apic. instead, software determines the vector (and therefore the priority) for each corresponding interrupt input signal. for each interrupt signal, the operating system can also specify the signal polarity (low active or high active), whether the interrupt is signaled as edges or levels, as well as the destination and delivery mode of the interrupt. the information in the redirection table is used to translate the corresponding interrupt pin information into an inter-apic message. the ioapic responds to an edge-triggered interrupt as long as the interrupt is wider than one clk cycle. the interrupt input is asynchronous. therefire, setup and hold times need to be guaranteed for at lease one rising edge of the clk input. once the interrupt is detected, a delivery status bit internal to the ioapic is set. a new edge on that interrupt input pin will not be recognized until the ioapic unit broadcasts the corresponding message over the apic bus and the message has been accepted by the destination(s) specified in the destination field. that new edge only results in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt wasn't already pending at the destination.) bits 31 ? 24 destination field (rw) ? if the destination mode of this entry is physical mode (bit 11 below = 0), bits [27:24] contain an apic id. if logical mode is selected (bit 11 below = 1), the destination field potentially defines a set of processors. bits [31:24] of the destination field specify the logical destination address. bits 27 through 24 of the destination field specify the 4-bit apic id. when destmod=1 (logical mode), destinations are identified by matching on the logical destination under the control of the destination format register and logical destination register in each local apic. bits 23 ? 0 reserved (always read 0) redirection table descriptor even doublewords even indexes 10h to 3eh 313029282726252423222120191817161514131211109876543210 reset dest reserved 0000000000000 0000000000 xxxxxxxx
290 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information redirection table descriptor odd doublewords odd indexes 11h to 3fh bits 31 ? 17 reserved (always read 0) bit 16 interrupt mask (rw) ? when this bit is 1, edge-sensitive interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). 0 = interrupt occurs (not masked) (default) 1 = mask interrupt level-asserts or negates occurring on a masked level-sensitive pin are ignored and have no side effects. changing the mask bit from unmasked to masked after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. it is software's responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. when this bit is 0, the interrupt is not masked. an edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination. bit 15 trigger mode (rw) ? the trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge (default) 1 = level bit 14 remote irr (ro) ? this bit is used for level-triggered interrupts. its meaning is undefined for edge-triggered interrupts. for level-triggered interrupts, this bit is set to 1 when local apic(s) accepts the level interrupt sent by the ioapic. the remote irr bit is set to 0 when an eoi message with a matching interrupt vector is received from a local apic. bit 13 interrupt input pin polarity (rw) ? this bit specifies the polarity of the interrupt signal. 0 = active high (default) 1 = active low bit 12 delivery status (ro) ? the delivery status bit contains the current status of the delivery of this interrupt. delivery status is read-only and writes to this bit (as part of a 32-bit word) do not affect this bit. 0 = idle (there is currently no activity for this interrupt) (default) 1 = send pending (the interrupt has been injected but its delivery is temporarily held up due to the apic bus being busy or the inability of the receiving apic unit to accept that interrupt at that time.) 313029282726252423 222120191817161514131211109876543210 reset reserved im t m ri rr p ol e ds m od e delivery mode interrupt vector 0000000000000 0000000000 xxxxxxxx
chapter 7 registers 291 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information bit 11 destination mode (rw) ? this field determines the interpretation of the destination field. when destmod=0 (physical mode), a destination apic is identified by its id. 0 = physical mode ioredtblx[27:24] = apic id 1 = logical mode ioredtblx[31:24] = set of processors bits 10 ? 8 delivery mode (rw) ? the delivery mode is a 3-bit field that specifies how the apics listed in the destination field should act upon reception of this signal. note that certain delivery modes only operate as intended when used in conjunction with a specific trigger mode. . bits 7 ? 0 interrupt vector (rw) ? the vector field is an 8-bit field containing the interrupt vector for this interrupt. vector values range from 10h to feh. table 83. delivery mode restrictions bits [10:8] mode description 000 fixed priority deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode for fixed-priority delivery mode can be edge or level. 001 lowest priority deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode for lowest priority. delivery mode can be edge or level. 010 smi a delivery mode equal to smi requires an edge-trigger mode. the vector information is ignored but must be programmed to all zeroes for future compatibility. 011 reserved 100 nmi deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi is treated as an edge- triggered interrupt, even if it is programmed as a level-triggered interrupt. for proper operation, this redirection table entry must be programmed to edge-triggered interrupt. 101 init deliver the signal to all processor cores listed in the destination by asserting the init signal. all addressed local apics will assume their init state. init is always treated as an edge-triggered interrupt, even if programmed otherwise. for proper operation, this redirection table entry must be programmed to edge-triggered interrupt. 110 reser ved 111 extint deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an externally connected (8259a-compatible) interrupt controller. the inta cycle that corresponds to this extint delivery is routed to the external controller that is expected to supply the vector. a delivery mode of extint requires an edge-trigger mode.
292 registers chapter 7 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 8 electrical data 293 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 8 electrical data 8.1 absolute ratings long-term reliability and functional integrity of the AMD-756 peripheral bus controller will be adversely affected if it is subjected to conditions exceeding the absolute ratings listed in table 84 . warning : stress above the parameters listed can cause permanent damage to the device. functional operation of this device should be restricted to the described conditions. 8.2 operating ranges the functional operation of the AMD-756 peripheral bus controller should be within the limits of the voltage and temperature parameters defined in table 85. table 84. absolute ratings parameter minimum maximum comments t case (under bias) -65 c +110 c t storage ? 65 c+150 c v dd3 ? 0.5 v 4.0 v v pin ? 0.5 v v dd3 +0.5v and < 4.0v table 85. operating ranges parameter minimum typical maximum comments v dd3 3.0 v 3.3 v 3.6 v (note 1) t case 0 c70 c note: 1. v dd3 is referenced from v ss
294 electrical data chapter 8 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 8.3 dc characteristics the dc characteristics of the AMD-756 peripheral bus controller are listed in the following tables. table 86. usb dc characteristics symbol parameter description preliminary data comments min max v bus supply voltage for powered host port 4.75 v 5.25 v i bus supply curretn for powered host port 500 ma v ol output low voltage 0.3 v i ol = 2.0 ma load v oh output high voltage 2.8 v 3.6 v i oh = -0.25 ma load v di differential input sensitivity 0.2 v v se single ended signal "0" 0.6 v 1.6 v i lo output leakage current ? 10 a 10 a 0 v in v dd3. c in transceiver capacitance 30 pf notes:
chapter 8 electrical data 295 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 87. ide dc charateristics table 88. ide driver types and required pull-ups symbol parameter description preliminary data comments min max v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage 0.5 v i ol = 4ma load v oh output high voltage 2.4 v i oh = .4 ma load i ol driver sink current 4 ma i oh driver source current 400 a c in input capacitance 25 pf c out output capacitance 25 pf notes: signal source driver type (see note 1) pull-up at host (see note 2) pull-up at each device (see note 2) notes reset host tp dd (15:0) bidir ts 3 dmarq device ts 5,6 k ? pd 4 dior- diow- host ts iordy device ts 1,0 k ? 5 csel host ground 10 k ? 6 dmack- host tp intrq device ts da (2:0) host tp pdiag- device ts 10 k ? cs0- cs1- host tp dasp- device oc 10 k ? notes: 1 ts=tri-state; oc=open collector; tp=totem-pole; pu=pull-up; pd=pull-down; vs=vendor specific 2 all resistor values are minimum (lowest) allowed. 3 devices shall not have a pull-up resistor on dd7. it is recommended that a host have a 10 k ? pull- down resistor and not a pull-up resistor on dd7 to allow a host to recognize the absence of a device at power-up. it is intended that this recommendation become mandatory in a future revision of this standard. 4 ata-3 defines this line to be tri-stated whenever the device is not selected or is not executing a dma data transfer. when enabled by dma transfer, it shall be driven high and low by the device. 5 this signal should only be enabled during dior/diow cycles to the selected device. 6 when used as csel, this line is grounded at the host and a 10 k ? pull-up is required at both devices.
296 electrical data chapter 8 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 89. isa bus dc charateristics table 90. pci bus dc charateristics symbol parameter description preliminary data comments min max v il input low voltage ? 0.50 v 0.8 v v ih input high voltage 2.0 v v dd3 +0.5 v note 1 v ol output low voltage 0.5 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 1.0-ma load i li input leakage current .4 ma i lo output leakage current 12 ma c out i/o capacitance (per slot) 20 pf notes: 1. v dd3 refers to the voltage being applied to v dd3 during functional operation. symbol parameter description preliminary data comments min max v il input low voltage ? 0.5 v 0.3v dd3 v v ih input high voltage 0.5v dd3 vv dd3 +0.5 v note 1 v ol output low voltage ad[31:]. c/be#[3:0], and preq# frame#, irdy#, trdy#, devel#, stop#, 2.0v 0.1v dd3 vi ol = 1.5 ma load v oh output high voltage 0.9v dd3 vi oh = -0.5 ma load i li input leakage current 10 a 0 < v in < v dd3 c in input capacitance 10 pf c clk pclk pin capacitance 5 pf 12 pf c out i/o capacitance 20 pf c clk clk capacitance 10 pf c tin test input capacitance (tdi, tms, trst) 10 pf c tout test output capacitance (tdo) 15 pf c tck tck capacitance 10 pf notes: 1. v dd3 refers to the voltage being applied to v dd3 during functional operation.
chapter 8 electrical data 297 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 8.4 power dissipation table 91 shows typical and maximum power dissipation of the AMD-756 peripheral bus controller during normal and reduced power states. the measurements are taken with pclk = 33 mhz, v dd3 = 3.3v. table 91. typical and maximum power dissipation clock control state typical ( note 1) maximum (note 2) comments normal (thermal power) tbd w tbd w note 3 notes: 1. typical power is measured during instruction sequences or functions associated with normal system opera- tion. 2. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states. 3. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the AMD-756 peripheral bus controller processor.
298 electrical data chapter 8 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 9 switching characteristics 299 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9 switching characteristics this section summarizes the AMD-756 peripheral bus controller signal switching characteristics. valid delay, float, setup, and hold timing specifications are listed. the setup and hold time requirements for the AMD-756 peripheral bus controller input signals presented here must be met by any device that interfaces with it to assure the proper operation of the AMD-756 peripheral bus controller. all signal timings are based on the following assumptions: n the target signals are input or output signals that are switching from logical 0 to 1, or from logical 1 to 0. n measurements are taken from the time the reference signal (hclk, pclk, or reset) passes through 1.5 v to the time the target signal passes through 1.5 v. n all signal slew rates are 1 v/ns, from 0 v to 3 v (rising) or 3 v to 0 v (falling). n parameters are within the operating range listed in table 84 on page 293. n the load capacitance (c l ) on each signal is 0 pf. n valid delay and float timings for output signals during functional operation are relative to the rising edge of the given clock.
300 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 9.1 osc switching characteristics figure 37. osc waveform table 92. osc switching characteristics for 14.3182-mhz bus symbol parameter description preliminary data figure comments min max frequency 14.3182 mhz t 1 clock period 67 ns 70 ns 37 t 2 clock high time 20 ns 37 t 3 clock low time 20 ns 37 note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz. t 2 2.0 v 1.5 v 0.8 v t 1 t 3
chapter 9 switching characteristics 301 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.2 pci interface timing table 93. pclk switching characteristics for 33-mhz pci bus figure 38. pclk waveform symbol parameter description preliminary data figure comments min max t 1 pclk cycle time 30 ns 38 t 2 pclk high time 11.0 ns 38 t 3 pclk low time 11.0 ns 38 t 4 pclk fall time 1 v/ns 4v/ns 38 t 5 pclk rise time 1 v/ns 4v/ns 38 pclk period stability 250 ps see note note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz. t 2 2.0 v 1.5 v 0.8 v t 5 t 1 t 4 t 3 2.4 v 0.4 v
302 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 39. setup, hold, and valid delay timing diagram table 94. pci interface timing symbol parameter description preliminary data figure comments min max t su ad[31:0] setup time 7 ns 39 pgnt# setup time 12 ns 39 frame#, stop#, trdy#, devsel#, irdy#, c/be[3:0]# setup time 7 ns 39 t h ad[31:0], frame#, stop#, trdy#, devsel#, irdy#, c/be[3:0]#, pgnt# hold time 1 ns 39 t vd ad[31:0], c/be[3:0]# valid delay 2 ns 15 ns 39 frame#, stop#, trdy#, devsel#, irdy# valid delay 2 ns 11 ns 39 preq# valid delay 2 ns 12 ns 39 t fd frame, #stop#, trdy#, devsel#, irdy#, c/be[3:0]# float delay 28 ns t lat preq# to pgnt# latency 2 clks note: measurements are taken with a 50pf load, unless otherwise noted. t su t h t vd t vd data in data out clk
chapter 9 switching characteristics 303 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.3 usb interface timing table 95. usbclk switching characteristics for usb bus symbol parameter description preliminary data figure comments min max frequency 48 mhz 48 mhz t 1 usbclk cycle time 20.8 ns 20.8 ns 40 t 2 usbclk high time 9.4 ns 40 t 3 usbclk low time 9.4 ns 40 12 m hz usbdata frequenc y 11.99 mb/s 12.01 mb/s 1.5 mhz usbdata frequency 1.48 mb/s 1.52 mb/s t 4 12 mhz usbdata data transition fall time 4 ns 20 ns 41 t 5 12 mhz usbdata data transition rise time 4 ns 20 ns 41 t 4 1.5 m hz usbdata data transition fall time 75 ns 300 ns 41 t 5 1.5 m hz usbdata data transition rise time 75 ns 300 ns 41 t 6 source differential skew 5 ns 41 t 6 receiver differential skew 10 ns 41 driver jitter 3 ns receiver jitter 25 ns single-ended driver skew 10 ns note: jitter frequency power spectrum peaking must occur at frequencies greater than (cclk frequency)/3 or less than 500 khz.
304 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 40. usbclk waveform figure 41. usb data waveform t 2 2.0 v 1.5 v 0.8 v t 1 t 3 t 5 90% 10% t 4 t 6 90% 10% t 6 d+ d- v oh v crs v ol
chapter 9 switching characteristics 305 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.4 isa interface timing figure 42. bclk waveform table 96. bclk switching characteristics for 8-mhz bus symbol parameter description preliminary data figure comments min max t 1 clock period 125 ns 42 t 2 clock high time 49 ns 42 t 3 clock low time 49 ns 42 t 4 clock rise time 4 ns 42 t 5 clock fall time 4 ns 42 note: t 2 2.0 v 1.5 v 0.8 v t 4 t 1 t 5 t 3
306 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 97. isa master interface timing symbol parameter description preliminary data figure comments min max t su1 la[23:20] setup to bale 150 ns 43 t su2 la[23:20] setup to memx# 173 ns 43 t su3 sa[19:0] setup to bale 37 ns 43 t su4 sa[19:0] setup to memx# 34 ns 43 t su5 sd[15:0] setup to memr# 24 ns 43 t su6 sd[15:0] setup to memw# ? 40 ns 43 t h1 la[23:17] hold from bale 26 ns 43 t h2 memcs16# hold from la[23:20] 0 ns 43 t h3 sa[19:0] hold from memx# 41 ns 43 t h4 sd[15:0] hold from memr# 0 ns 43 t h5 sd[15:0] hold from memw# 45 ns 43 t vd1 la[23:17] to memcs16# valid delay 94 ns 43 t vd2 memr# to sd[15:0] valid delay 150 ns 43 t vd3 memx# to bale valid delay 44 ns 43 t vd4 memx# to iochrdy valid delay 78 ns 43 t vd5 memx# to smemx 16 ns 43 t vd6 sa[19:0], sbhe# to memcs16# valid delay 35 ns 43 t pw1 bale pulse width (high) 50 ns 43 t pw2 iochrdy inactive pulse width 120 ns 43 t pw3 memx# active pulse width (low) 225 ns 43 t pw4 memx# inactive pulse width (high) 163 ns 43 t fd1 memr# to sd[15:0] float delay 41 ns 43 t fd2 memw# to sd[15:0] float delay 105 ns 43 note: measurements are taken with no load.
chapter 9 switching characteristics 307 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 43. isa master interface timing t pw1 t su3 t h1 t pw1 t su2 t h2 t su4 t h3 t su6 t su5 t h4 t h5 t pw4 t pw2 t vd3 t vd5 t vd6 t vd1 t vd4 t vd2 t fd1 t fd2 bale la[23:17] sa[19:0], sbhe# memr#, memw# smemr#, smemw# memcs16# iochrdy sd[15:0] read sd[15:0] write t pw3 t su1
308 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 98. isa 8-bit slave interface timing symbol parameter description preliminary data figure comments min max t su1 aen setup to bale 111 ns 44 t su2 aen setup to iox# 111 ns 44 t su3 sa[19:0] setup to bale 37 ns 44 t su4 sa[19:0] setup to iox# 100 ns 44 t su5 sd[15:0] setup to ior# 24 ns 44 t su6 sd[15:0] setup to iow# ? 40 ns 44 t h1 aen hold to iox# 41 ns 44 t h2 sa[19:0] hold to iox# 41 ns 44 t h3 sd[15:0] hold to ior# 0 ns 44 t h4 sd[15:0] hold to iow# 45 ns 44 t vd1 ior# to sd[15:0] valid delay 500 ns 44 t vd2 iox# to bale valid delay 44 ns 44 t vd3 iox# to iochrd valid delay 366 ns 44 t vd4 sa[19:0] to iocs16# valid delay 91 ns 44 t pw1 bale pulse width 50 ns 44 t pw2 iochrdy inactive pulse width 120 ns 44 t pw3 iox# active pulse width 160 ns 44 t pw4 iox# inactive pulse width 163 ns 44 t fd1 ior# to sd[15:0] float delay 41 ns 44 t fd2 iow# to sd[15:0] float delay 105 ns 44 note: measurements are taken with no load.
chapter 9 switching characteristics 309 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 44. isa 8-bit slave interface timing t su4 t pw1 t su1 t su3 t pw1 t su2 t h1 t h2 t pw3 t su6 t su5 t h3 t h4 t pw4 t pw2 t vd2 t vd4 t vd3 t vd1 t fd2 bale aen sa[19:0], sbhe# ior#, iow# iocs16# iochrdy sd[15:0] r sd[15:0] w t fd1
310 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 99. isa 16-bit slave interface timing symbol parameter description preliminary data figure comments min max t su1 aen setup to bale 150 ns 45 t su2 aen setup to iox# 150 ns 45 t su3 sa[19:0] setup to iox# 34 ns 45 t su4 sa[19:0] setup to bale 37 ns 45 t su5 sd[15:0] setup to ior# 24 ns 45 t su6 sd[15:0] setup to iow# ? 40 ns 45 t h1 aen hold from iox# 26 ns 45 t h2 iocs16# hold from sa[19:0] 0 ns 45 t h3 sa[19:0] hold from iox# 41 ns 45 t h4 sd[15:0] hold from ior# 0 ns 45 t h5 sd[15:0] hold from iow# 45 ns 45 t vd1 iox# to iochrdy valid delay 78 ns 45 t vd2 iox# to bale valid delay 44 ns 45 t vd3 iox# to iocs16# valid delay 16 ns 45 t vd4 sa[19:0] to iocs16# valid delay 35 ns 45 t vd5 ior# to sd[15:8] valid delay 1.5 ns 8.5 ns 45 t pw1 bale pulse width 50 ns 45 t pw2 iochrdy inactive pulse width 120 ns 45 t pw3 iox# active pulse width 160 ns 45 t pw4 iox# inactive pulse width 163 ns 45 t fd1 ior# to sd[15:0] float delay 41 ns 45 t fd2 iow# to sd[15:0] float delay 105 ns 45 note: measurements are taken with no load.
chapter 9 switching characteristics 311 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 45. isa 16-bit slave interface timing t pw1 t su1 t su4 t pw1 t su2 t h1 t su3 t h3 t h2 t pw3 t su6 t su5 t h4 t h5 t pw4 t pw2 t vd2 t vd3 t vd4 t vd1 t vd5 t fd1 t fd2 bale aen sa[19:0],sbhe# ior#, iow# iocs16# iochrdy sd[15:0] r sd[15:0] w
312 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information . table 100. isa master-to-pci access timing symbol parameter description preliminary data figure comments min max t su1 la[23:17] setup to memx# 23 ns 46 t su2 sa[19:0] setup to memx# 23 ns 46 t su3 sd[15:0] setup to memr# 15 ns 46 t su4 sd[15:0] setup to memw# ? 54 ns 46 t h1 la[23:17] hold from memx# 30 ns 46 t h2 sa[19:0] hold from memx# 30 ns 46 t h3 sd[15:0] hold from memr# 0 ns 46 t h4 sd[15:0] hold from memw# 14 ns 46 t vd1 iochrdy to sd[15:0] valid delay 69 ns 46 t vd2 la[23:17] to memcs16# valid delay 31 ns 46 t vd3 memx# to iochrdy valid delay 85 ns 46 t pw1 iochrdy inactive pulse width 120 ns 46 t pw2 memx# active pulse width 214 ns 46 t pw3 memx# inactive pulse width 92 ns 46 t fd1 memr# to sd[15:8] float delay 55 ns 46 t fd2 memw# to sd[15:8] float delay 50 ns 46 note: measurements are taken with no load.
chapter 9 switching characteristics 313 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 46. isa master-to-pci access timing t su1 t h1 t su2 t h2 t pw2 t su3 t h3 t su4 t h4 t pw3 t pw1 t vd4 t vd3 t vd1 t fd1 la[23:17] sa[19:0], sbhe# memr#, memw# memcs16# iochrdy sd[15:0] r sd[15:0] w t fd2
314 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information . figure 47. other isa master timing table 101. other isa master timing symbol parameter description preliminary data figure comments min max t vd1 dreq to dack# valid delay 240 ns 47 t vd2 dack# to address, data, and control valid delay 71 n s 47 t fd1 dack# to address, data, and control float delay 0 ns 47 note: measurements are taken with no load. t vd1 t fd1 t vd2 t fd1 t vd2 t fd1 t vd2 t fd1 t vd2 t fd1 t vd2 dreq dack# aen la[23:17] sa[15:0], sbhe# memr#, memw# ior#, iow# sd[15:0]
chapter 9 switching characteristics 315 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.5 dma interface timing table 102. dma read cycle timing symbol parameter description preliminary data figure comments min max t su1 aen setup to iow# 111 ns 48 t su2 dack# setup to iow# 312 ns 48 t su3 memr# setup to iow# ? 26 ns 48 t su4 sa[19:0],la[23:20] setup to memr# 99 ns 48 t su5 sd[15:0] setup to iow# 225 48 t su6 tc setup to iow# 511 48 t h1 aen hold from iow# 41 ns 48 t h2 dack# hold from iow# 155 ns 48 t h3 memr# hold from iow# 40 ns 48 t h4 memr# hold from iochrdy 120 ns 48 t h5 sa[19:0], la[23:20] hold from memr# 51 ns 48 t h6 sd[15:0] hold from iow# 36 ns 48 t h7 tc hold from iow# 71 ns 48 t vd1 iow# to dreq inactive valid delay 315 ns 48 t vd2 memr# to smemr# valid delay 15 ns 48 t vd3 memr# to iochrdy valid delay 315 ns 48 t pw1 iochrdy inactive pulse width 125 ns 48 t pw2 iow# active pulse width 495 ns 48 t pw3 iow# inactive pulse width 465 ns 48 t pw4 memr# active pulse width 495 ns 48 t pw5 memr# inactive pulse width 465 ns 48 t pw6 tc active pulse width 700 ns 48 note: measurements are taken with no load.
316 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 48. dma read cycle timing t su1 t h1 t su2 t h2 t su4 t h5 t su4 t h5 t h5 t pw4 t su3 t pw5 t h3 t su5 t pw2 t h6 t pw3 t su6 t h7 t pw1 t pw6 t vd1 t vd2 t vd3 dreq aen dack# la[23:20] sa[19:0], sbhe# memr# smemr# iow# iochrdy sd[15:0] tc t h4
chapter 9 switching characteristics 317 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 103. dma write cycle timing symbol parameter description preliminary data figure comments min max t su1 aen setup to ior# 111 ns 49 t su2 dack# setup to ior# 73 ns 49 t su3 sa[19:0],la[23:20] setup to memw# 99 ns 49 t su4 tc setup to ior# 511 ns 49 t h1 aen hold from ior# 41 ns 49 t h2 dack# hold from ior# 100 ns 49 t h3 memw# hold from ior# 40 ns 49 t h4 sa[19:0], la[23:20] hold from memw# 51 ns 49 t h5 sd[15:0] hold from ior# 0 ns 49 t h6 tc hold from ior# 71 ns 49 t vd1 ior# to drq valid delay 558 ns 49 t vd2 ior# to memw# valid delay 230 ns 49 t vd3 ior# to sd[15:0] valid delay 237 ns 49 t vd4 memw# to iochrdy valid delay 315 ns 49 t vd5 memw# to smemw# valid delay 15 ns 49 t pw1 iochrdy active pulse width 125 ns 49 t pw2 ior# active pulse width 760 ns 49 t pw3 ior# inactive pulse width 160 ns 49 t pw4 memw# active pulse width 495 ns 49 t pw5 memw# inactive pulse width 465 ns 49 t pw6 tc active pulse width 700 ns 49 note: measurements are taken with no load.
318 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 49. dma write cycle timing t su1 t h1 t su2 t h2 t su3 t h4 t su3 t h4 t h4 t pw4 t pw5 t h3 t pw2 t h5 t pw3 t h5 t su4 t h6 t pw1 t pw6 t vd1 t vd2 t vd5 t vd4 t vd3 dreq aen dack# la[23:20] sa[19:0], sbhe# memw# smemw# ior# iochrdy sd[15:0] tc
chapter 9 switching characteristics 319 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 104. type f dma interface timing symbol parameter description preliminary data figure comments min max t su1 sd[15:0] setup to iow# 70 ns 50 t su2 tc setup to final iox# 40 ns 50 t h1 dack# hold from ior# 30 ns 50 t h2 dack# hold from iow# 30 ns 50 t h3 dreq hold from ior# 82 ns 50 t h4 dreq hold from iow# 82 ns 50 t h5 sd[15:0] hold from ior# 2 ns 50 t h6 tc hold from iow# 0 ns 50 t vd1 aen to ior# valid delay 111 ns 50 t vd2 aen to iow# valid delay 111 ns 50 t vd3 dack# to ior# valid delay 77 ns 50 t vd4 dack# to iow# valid delay 77 ns 50 t vd5 ior# to sd[15:0]valid delay 96 ns 50 t pw1 ior# active pulse width 110 ns 50 t pw2 ior# inactive pulse width 115 ns 50 t pw3 iow# active pulse width 110 ns 50 t pw4 iow# inactive pulse width 115 ns 50 t fd1 ior# to sd[15:8] float delay 61 ns 50 note: measurements are taken with no load.
320 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 50. type f dma interface timing t h4 t h3 t h2 t h1 t pw3 t h6 t su1 t pw4 t su2 t h6 t su1 t pw1 t pw2 t h5 t h5 t vd2 t vd4 t vd1 t vd3 t vd5 t vd5 t fd1 dreq aen dack# iow# memr# sd[15:0] ior# memw# sd[15:0]r tc
chapter 9 switching characteristics 321 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.6 eide interface timing table 105. eide pio symbol description mode 0 mode 1 mode 2 mode 3 mode 4 t cyc1 cycle time (diow/r# to diow/r#) min 600 383 240 180 120 t rec1 diox# recovery time min ??? 70 25 t su1 da[2:0] setup to diox# max 70 50 30 30 25 t su2 ddata[15:0] read setup to dior# min 50 350 20 20 20 t su3 ddata[15:0] read setup to pclk min 10 10 10 10 10 t su4 ddata[15:0] write setup to diow# min 60 45 30 30 20 t su5 iordy setup to pclk min 20 20 20 20 20 t h1 ddata[15:0] read hold from dior#min55555 t h2 ddata[15:0] read hold from pclkmin44444 t h3 ddata[15:0] write hold from diow# min 30 20 15 10 10 t h4 iordy# hold from pclk min55555 t vd1 pclk to da[2:0], dcsx# valid delaymin22222 t vd1 pclk to da[2:0], dcsx# valid delay max 20 20 20 20 20 t vd2 pclk to ddata[15:0] valid delaymin22222 t vd2 pclk to ddata[15:0] valid delay max 20 20 20 20 20 t vd3 pclk to soe#, master# valid delaymin22222 t vd3 pclk to soe#, master# valid delay max 20 20 20 20 20 t pw1 8-bit diox# pulse width min 290 290 290 80 70 t pw1 16-bit diox# pulse width min 165 125 100 80 70 note: all timings are in nanoseconds and reference figure 51 .
322 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 51. e i d e pio t su1 t vd1 t cyc1 t pw1 t rec1 t su2 t su3 t h1 t h2 t su4 t vd2 t h3 t vd3 t vd3 t su5 t h4 pclk da[2:0], dior#, diow# ddata [15:0] (read) ddata [15:0] (write) soe# master# iordy dcsx#
chapter 9 switching characteristics 323 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 106. eide dma symbol description single-word multi-word mode 0 mode 1 mode 2 mode 0 mode 1 mode 2 t cyc1 cycle time (ddack# to ddack#) min 960 480 240 480 150 120 t su1 ddack# setup to diox# min000000 t su2 ddata [15:0] setup to iowr# min 250 100 35 100 30 20 t su3 ddata[15:0] setup to pclk min101010101010 t su4 ddrq setup to pclk min101010101010 t h1 ddack# hold from diox# min0002055 t h2 ddata [15:0] hold from iord#min555555 t h3 ddata [15:0] hold from iowr#min555555 t h4 ddata[15:0] hold from pclk min444444 t h5 ddrq hold from pclk min222222 t vd1 ddrq to ddack# valid delay max 200 100 80 35 t vd2 ddrq to dior# valid delay min 120 40 35 t vd3 ddrq to diow# valid delay min 40 40 35 t vd4 pclk to ddack# valid delay min222222 t vd4 pclk to ddack# valid delay max 20 20 20 20 20 20 t vd5 pclk to ddata[15:0] valid delaymin222222 t vd5 pclk to ddata[15:0] valid delay max 20 20 20 20 20 20 t vd6 pclk to master#, soe# valid delay min222222 t vd6 pclk to master#, soe# valid delay max202020202020 t pw1 diox# active pulse width min 480 240 120 215 80 70 t pw2 dior# inactive pulse width min ??? 50 50 25 t pw3 diow# inactive pulse width min ??? 215 50 25 note: all timings are in nanoseconds and reference figure 52
324 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 52. eide dma t vd6 t vd1 t su4 t h5 t cyc1 t vd4 t pw1 t su1 t vd2 t pw2 t h1 t su3 t h4 t h2 t pw1 t su1 t vd3 t wp3 t h1 t su2 t vd5 t h3 pclk master#, soe# ddrq ddack# dior# ddata [15:0] (read) diow# ddata [15:0] (write)
chapter 9 switching characteristics 325 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 9.7 ultra dma-33 ide bus interface timing table 107. ultra dma-33 ide bus interface timing symbol parameter description preliminary data figure comments min max t dh1 data hold time for read initial (rise) 6 ns 28 t dvh5 data hold time for write terminating 6 ns 32 t dvh2 data hold time for write initial (fall) 18 ns 31 t dvh2 data hold time for write initial 18 ns 31 t dvh4 data hold time for read terminating 6 ns 29 t rdh data hold time during pio and dma read 20 ns 25 t wdh data hold time during pio and dma write 20 ns 25 t ds1 data setup time for read initial 5 ns 27 t dvs2 data setup time for write initial (fall) 43 ns 31 t dvs2 data setup time for write initial 42 ns 31 t dvs4 data setup time for read terminating 34 ns 29 t dvs5 data setup time for write terminating 34 ns 32 t rds data setup time during pio and dma read 30 ns 25 t wds data setup time during pio and dma write 30 ns 25 t env1 envelope time for read initial 20 ns 70 ns 27 t env2 envelope time for write initial (rise) 20 ns 70 ns 31 t li4 limited interlock time (to stop) 0 ns 150 ns 29 t li4 limited interlock time (to host dmardy) 0 ns 150 ns 29 t li5 limited interlock time (to stop) 0 ns 150 ns 32 t li5 limited interlock time (to host strobe) 0 ns 150 ns 32 t li5 limited interlock time 0 ns 150 ns 25 t mli5 limited interlock time with minimum 20 ns 32 t mli6 limited interlock time with minimum 20 ns 30 t rfs ready to final strobe time 50 ns 28 t rp ready to pause time 100 ns 28 t za4 delay time required for output drives turning on 20 ns 29 t za6 delay time required for output drives turning on 34 ns 32 t 2 delay time of pclk to dcs3#, dcs1# 2 ns 20 ns 25 t 3 delay time of pclk to da2-da0 2 ns 20 ns 25 t 4 delay time of pclk to diow# 2 ns 20 ns 25 t 5 delay time of pclk to dior# 2 ns 20 ns 25
326 switching characteristics chapter 9 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 10 pin designations 327 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 10 pin designations 10.1 pin designation table the 272 pins of the AMD-756 peripheral bus controller are listed in the table 108, grouped according to their functions.
328 pin designations chapter 10 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information table 108. functional grouping pci bus interface isa bus control eide interface pin name pin no. pin name pin no. pin name pin no. pin name pin no. ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 c/be0# c/be1# c/be2# c/be3# devsel# frame# idsel irdy# par pcirst# pclk pgnt# pirqa# pirqb# pirqc# pirqd# preq# serr# stop# trdy# c6 b6 a7 a6 c7 d6 b7 d7 b8 c8 b9 d8 a9 b10 a10 b11 d12 c12 b14 c13 b15 a14 a15 b16 c14 a16 d14 b17 c15 a17 b18 a18 a8 c9 a13 d13 c10 c11 b13 d10 d9 d15 a20 a19 c16 c18 d16 c17 b19 a11 b12 a12 aen bale bclk dack0# dack1# dack2# dack3# dack5# dack6# dack7# drq0 drq1 drq2 drq3 drq5 drq6 drq7 iochck# iochrdy iocs16# ior# iow# irq3 irq4 irq5 irq6 irq7 irq9 irq10 irq11 irq12 irq14 irq15 la17 la18 la19 la20 la21 la22 la23 master# memcs16# memr# memw# osc refresh# rom_kbcs# g3 b5 v2 k2 n3 v8 k3 m2 p2 t2 l2 p3 e4 l3 n2 r2 u2 a4 g4 d2 k4 j3 v7 v6 v5 v4 u5 c4 e2 f2 g2 j2 h2 j1 h1 g1 f1 e1 d1 c1 w1 c2 k1 l1 u20 r3 n20 rstdrv sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 sa16 sbhe# sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 smemr# smemw# spkr tc a5 b2 a1 a2 u10 u9 u8 u7 u6 v3 u3 t3 t4 r4 p4 m3 m4 h3 b1 f3 f4 e3 d3 c3 b3 b4 a3 m1 n1 p1 r1 t1 u1 v1 y1 j4 h4 v11 v9 daddrp2 daddrp1 daddrp0 daddrs2 daddrs1 daddrs0 dcs1p# dcs1s# dcs3p# dcs3s# ddackp# ddacks# ddatap0 ddatap1 ddatap2 ddatap3 ddatap4 ddatap5 ddatap6 ddatap7 ddatap8 ddatap9 ddatap10 ddatap11 ddatap12 ddatap13 ddatap14 ddatap15 ddatas0 ddatas1 ddatas2 ddatas3 ddatas4 ddatas5 ddatas6 ddatas7 ddatas8 ddatas9 ddatas10 ddatas11 ddatas12 ddatas13 ddatas14 ddatas15 ddrqp ddrqs diorp# diors# diowp# diows# drdyp# drdys# v18 y17 y18 y19 w17 w18 w19 v19 y20 w20 y16 w16 y11 y10 y9 y8 w7 y5 w4 y2 w2 y3 w5 y6 w8 w9 w10 w11 u18 v16 v15 v14 v13 u13 v12 u12 w3 y4 w6 y7 u14 u15 u16 v17 y12 w12 y14 w14 y13 w13 y15 w15 * multifunction pin
chapter 10 pin designations 329 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 108. functional grouping (continued) usb interface miscellaneous keyboard interface pin name pin no. pin name pin no. pin name pin no. pin name pin no. usbclk usbp3 usbp2 usbp1 usbp0 usbn3 usbn2 usbn1 usbn0 usboc1#(irq12) usboc0# c19 d18 d20 e18 e20 d19 e17 e19 f17 g2 b20 usbirq (picclk) kbcirq (picd0#) pitirq (picd1#) sciirq (wsc#) spare1 test# t17 r20 r19 n18 c5 d5 kbck(ka20g) kbdt (kbrc#) keylock(dbrdy) msck(ekirq1) msdt(ekirq12) k17 j20 k19 k18 k20 power & ground rtc cpu interface power management pin name pin no. pin name pin no. pin name pin no. pin name pin no. gnd gnd-usb v dd3 v dd_ref v dd_rtc v dd_soft v dd_usb j9 j10 j11 j12 k9 k10 k11 k12 l9 l10 l11 l12 m9 m10 m11 m12 f18 d4 d11 d17 l4 l17 u4 u11 u17 n4 f19 j19 c20 rtcxin rtcxout f20 g17 a20m# cpurst ferr# ignne# init intr nmi smi# stpclk# m18 n19 t19 t18 t20 r17 r18 m17 n17 c32khz cachezz (pnpirq1) cpusleep# (pnpcs0#) cpustop# (pnpcs1#) dcstop# (pnpirq2) extsmi# (bmreq#) flagrd# (pnpdak#) flagwr (pnpdrq) intirq8# (sqwave) pcistop# (pnpirq0) pme# pwrbtn# pwrgd pwron# ri# serirq (msirq) smbusc smbusd slpbtn# (pmirq1) (extirq8#) suspend# therm# (pmirq0) v20 p20 l18 p19 l19 h19 m20 l20 v10 p18 h20 h18 j18 j17 g18 p17 g19 g20 h17 m19 u19 * multifunction pin
330 pin designations chapter 10 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 10.1.1 state of pins at reset table 110 shows reference data about each of the AMD-756 peripheral bus controller pins. the reset column lists the state of the pin while the its power plane is being reset. the post reset column lists the state of the pin immediately after that reset. the pos column lists the state of the pin while in the clock-controlled power on suspend state. table 109. i/o cell types name description input input signal only. output output signal only. this includes outputs that are capable of being in the high-impedance state. od open drain output. these pins are driven low, but pulled up by external circuitry. i/o input or output signal. i/od input or open-drain output. w/h with hysteresis on the input. analog analog pins table 110. state of pins at reset pin name group cell power plane iol/ioh reset post reset pos notes a20m# cpu od vdd3 12 ma 3-state 3-state 3-state see 8 ad[31:0] pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state aen isa output vdd3 4 / -4 ma low low low bale isa output vdd3 see 3 high low low bclk isa output vdd3 see 3 active active active c32khz sm i/o vdd3 4 / -4 ma low low see note defaults to gpio output; see 5 cache_zz sm i/o vdd3 4 / -4 ma low low see note defaults to gpio output; see 5 c/be#[3:0] pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state cpurst# cpu od vdd3 12 ma active active low see 8 cpusleep# sm i/o vdd3 4 / -4 ma high high see note defaults to gpio output; see 5 cpustop# sm i/o vdd3 4 / -4 ma high high see note defaults to gpio output; see 5 dack[7:5,3:0]# isa output vdd3 4 / -4 ma high high high
chapter 10 pin designations 331 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information daddrp[2:0] ide i/o vdd3 4 / -4 ma input low low see 6 daddrs[2:0] ide output vdd3 4 / -4 ma low low low see 7 dcs1p# ide i/o vdd3 4 / -4 ma input high high see 6 dcs1s# ide output vdd3 4 / -4 ma high high high see 7 dcs3p# ide output vdd3 4 / -4 ma high high high dcs3s# ide output vdd3 4 / -4 ma high high high see 7 dcstop# sm i/o vdd3 4 / -4 ma high high see note defaults to gpio output; see 5 ddackp# ide output vdd3 4 / -4 ma high high high ddacks# ide output vdd3 4 / -4 ma high high high see 7 ddatap[15:0] ide i/o vdd3 4 / -4 ma 3-state 3-state low ddatas[15:0] ide i/o vdd3 4 / -4 ma 3-state 3-state low see 7 ddrqp ide input vdd3 - - - - ddrqs ide input vdd3 - - - - see 7 devsel# pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state diorp# ide output vdd3 4 / -4 ma high high high diors# ide output vdd3 4 / -4 ma high high high see 7 diowp# ide output vdd3 4 / -4 ma high high high diows# ide output vdd3 4 / -4 ma high high high see 7 drdyp# ide input vdd3 - - - drdys# ide input vdd3 - - - see 7 drq[7:5,3:0] isa input vdd3 - - - extsmi# sm i/o vdd_soft 4 / -4 ma input input active muxed with gpio12 and bmreq# frame# pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state ferr# cpu input w/h vdd3 - - - flagwr sm i/o vdd3 4 / -4 ma low low see note defaults to gpio output; see 5 flagrd# sm i/o vdd3 4 / -4 ma high high see note defaults to gpio output; see 5 gnd[15:0] p&g analog low low low gnd_usb p&g analog low low low idsel pci input vdd3 - - - ignne# cpu od vdd3 12 ma 3-state 3-state 3-state see 8 init# cpu od vdd3 12 ma low low low see 8 table 110. state of pins at reset (continued) pin name group cell power plane iol/ioh reset post reset pos notes
332 pin designations chapter 10 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information intirq8# sm i/o vdd3 4 / -4 ma high high see note defaults to gpio output; see 5 intr cpu od vdd3 12 ma low low low see 8 iochk# isa input vdd3 - - - iochrdy isa i/od vdd3 see 3 3-state 3-state 3-state iocs16# isa input vdd3 - - - ior# isa i/o vdd3 see 3 high high high iow# isa i/o vdd3 see 3 high high high irdy# pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state irq12 isa input vdd3 - - - muxed with smbalert#, usboc1# irq [15,14,11:9,7:3] isa input vdd3 - - - kbdt kbdc i/o vdd3 4 / -4 ma see note see note active see 1 kbck kbdc i/o vdd3 4 / -4 ma see note see note active see 1 keylock kbdc i/o vdd3 4 / -4 ma input input active muxed with gpio13, prdy la[23:17] isa i/o vdd3 see 3 3-state low last state master# isa input vdd3 - - - memcs16# isa i/od vdd3 see 3 3-state 3-state 3-state memr# isa i/o vdd3 see 3 high high high memw# isa i/o vdd3 see 3 high high high msdt kbdc i/o vdd3 4 / -4 ma see note see note active see 1 msck kbdc i/o vdd3 4 / -4 ma see note see note active see 1 nmi cpu od vdd3 12 ma low low low see 8 osc isa input vdd3 - - - par pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state pcirst# pci output vdd3 4 / -4 ma active active high pcistop# sm i/o vdd3 4 / -4 ma high high see note defaults to gpio output; see 5 pclk pci input vdd3 - - - must be active during reset pgnt# pci input vdd3 - - - pirq[a,b,c,d]# pci input vdd3 - - - table 110. state of pins at reset (continued) pin name group cell power plane iol/ioh reset post reset pos notes
chapter 10 pin designations 333 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information pme# sm input vdd_soft - - - preq# pci output vdd3 4 / -4 ma high high high pwrbtn# sm input vdd_soft - - active pwrgd sm input vdd_soft - - - pwron# sm od vdd_soft 4 ma low low active refresh# isa i/o vdd3 see 3 high high active ri# sm i/o vdd_soft 4 / -4 ma input input active muxed with gpio14 rom_kbcs# isa i/o vdd3 4 / -4 ma input high high see 1 rstdrv isa output vdd3 see 3 active active low rtcx_in rtc analog vdd_rtc active active active rtcx_out rtc analog vdd_rtc active active active sa[16:0] isa i/o vdd3 see 3 3-state active last state see 4 sbhe# isa i/o vdd3 see 3 3-state active last state sd[15:0] isa i/o vdd3 see 3 3-state active 3-state serirq sm i/o vdd3 4 / -4 ma input input see note defaults to gpio input; see 5 serr# pci input vdd3 - - - smbusc sm i w/h / od vdd_soft 4 / -4 ma 3-state 3-state active muxed with gpio0 smbusd sm i w/h / od vdd_soft 4 / -4 ma 3-state 3-state active muxed with gpio1 smemr# isa output vdd3 see 3 high high high smemw# isa output vdd3 see 3 high high high smi# cpu od vdd3 12/-12 ma 3-state 3-state 3-state see 8 spare1 misc - vdd3 - - - - spkr isa i/o vdd3 12 / -12 ma input low last state see 2 slpbtn# sm i/o vdd_soft 4 / -4 ma - - active muxed with gpio3, pmirq1, and extirq8# stop# pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state stpclk# cpu od vdd3 12/-12 ma 3-state 3-state active see 8 suspend# sm i/o vdd3 4 / -4 ma high high active muxed with gpio4 tc isa output vdd3 see 3 low low low test# misc input vdd3 - - - therm# sm i/o vdd3 4 / -4 ma input input active muxed with gpio2, pmirq0 table 110. state of pins at reset (continued) pin name group cell power plane iol/ioh reset post reset pos notes
334 pin designations chapter 10 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information trdy# pci i/o vdd3 4 / -4 ma 3-state 3-state 3-state usbclk usb input vdd3 - - - usbn[3:0] usb analog vdd_usb 3-state 3-state active usboc0# usb input vdd3 - - active usbp[3:0] usb analog vdd_usb 3-state 3-state active vdd3[7:0] p&g analog - - - vdd_ref p&g analog - - - vdd_rtc p&g analog - - - vdd_soft p&g analog - - - vdd_usb p&g analog - - - notes: 1. during reset, the kbck, kbdt, msck, and msdt pins ? default is determined by the state of the rom_kbcs# signal which selects between an internal or external keyboard controller. if the internal keyboard controller is selected, then kbck and msck are lo w outputs and kbdt and msdt are inputs. if the external keyboard controller is selected, then kbck (ka20g), msck (irq1), and msdt (irq12) are inputs and kbdt (kbrc#) is a high output. after reset, all the outputs are functional. during pos, these pins remain functional. 2. spkr is only an input during pwrgd reset. the state of spkr is latched in function 3 offset 48 (but does not control anythin g). 3. these i/o current for these pins is can be selected to be either 24 or 12 milliamps (source and sink), by function 0, offset 49, bit 3, isa12ma. 4. sa[15:0] can be multiplexed with the muxed ide controller ? s ddatam[15:0] pins during operation. 5. these pins can be individually configured to be either pnp controls, gpios, or power management pins. as pnp pins, these are held in the inactive state during pos. as gpio outputs, these just stay in their last state during pos. as power management pin s, these pins perform specific functions during c2, c3, and pos as shown in the system management section of this document. 6. daddrp[2:0] and dcs1p# are only inputs during pwrgd reset. their states are latched in function 3 offset 48. 8. the i/o cell for the output cpu signals, a20m#, cpurst, ignne#, intr, init, nmi, smi#, and stpclk#, can be selected by the state of the spkr pin at reset to be either open-drain or normal. also, picd0#, picd1#, wsc#, and picclk are all muxed with internal AMD-756 peripheral bus controller interrupts, as selected by function 0, offset 49, bit 6, rvlint. as AMD-756 peripher al bus controller interrupts, they are normal outputs that are driven both high and low. table 110. state of pins at reset (continued) pin name group cell power plane iol/ioh reset post reset pos notes
chapter 10 pin designations 335 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 10.1.2 AMD-756 ? peripheral bus controller pin diagram figure 53 shows the pin diagram for the AMD-756 peripheral bus controller. figure 53. AMD-756 ? peripheral bus controller pin diagram 1234567891011121314151617181920 a sa1 sa2 sd7 iochk# rstdrv ad3 ad2 c/be#0 ad12 ad14 serr# trdy# c/be#2 ad21 ad22 ad25 ad29 ad31 pgnt# pclk b sbhe# sa0 sd5 sd6 bale ad1 ad6 ad8 ad10 ad13 ad15 stop# idsel ad18 ad20 ad23 ad27 ad30 preq# usboc0# c la23 mem- cs16# sd4 irq9 spare1 ad0 ad4 ad9 c/be#1 devsel# frame# ad17 ad19 ad24 ad28 pirqa# pirqd# pirqb# usbclk vdd_usb d la22 iocs16# sd3 vdd3 test# ad5 ad7 ad11 par irdy# vdd3 ad16 c/be#3 ad26 pcirst# pirqc# vdd3 usbp3 usbn3 usbp2 e la21 irq10 sd2 drq2 usbn2 usbp1 usbn1 usbp0 f la20 irq11 sd0 sd1 usbn0 gnd_ usb vdd_rtc rtcx_in g la19 irq12 aen iochrdy rtcx_ out ri# smbusc smbusd h la18 irq15 sa16 smemw# slpbtn# pwr- btn# extsmi# pme# j la17 irq14 iow# smemr# gnd gnd gnd gnd pwron# pwrgd vdd_ soft kbdt k memr# dack0# dack3# ior# gnd gnd gnd gnd kbck msck keylock msdt l memw# drq0 drq3 vdd3 gnd gnd gnd gnd vdd3 cpu- sleep# dcstop# flagwr m sd8 dack5# sa14 sa15 gnd gnd gnd gnd smi# a20m# sus- pend# flagrd# n sd9 drq5 dack1# vdd_ref stpclk# wsc# cpurst# rom_ kbcs# p sd10 dack6# drq1 sa13 serirq pcistop# cpu- stop# cache _zz r sd11 drq6 refresh # sa12 intr nmi picd1# picd0# t sd12 dack7# sa10 sa11 picclk ignne# ferr# init# u sd13 drq7 sa9 vdd3 irq7 sa7 sa6 sa5 sa4 sa3 vdd3 ddatas7 ddatas5 ddatas12 ddatas13 ddatas14 vdd3 ddatas0 therm# osc v sd14 bclk sa8 irq6 irq5 irq4 irq3 dack2# tc intirq8# spkr ddatas6 ddatas4 ddatas3 ddatas2 ddatas1 ddatas15 daddrp2 dcs1s# c32khz w master# ddatap8 ddatas8 ddatap6 ddatap10 ddatas10 ddatap4 ddatap12 ddatap13 ddatap14 ddatap15 ddrqs diows# diors# drdys# ddacks# daddrs1 daddrs0 dcs1p# dcs3s# y sd15 ddatap7 ddatap9 ddatas9 ddatap5 ddatap11 ddatas11 ddatap3 ddatap2 ddatap1 ddatap0 ddrqp diowp# diorp# drdyp# ddackp# daddrp1 daddrp0 daddrs2 dcs3p#
336 pin designations chapter 10 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information 10.1.3 multiplexed pins table 111 shows pins that are multiplexed with other functions that can be selected by the systemboard designer. shaded areas are the power-up defaults from the pwrgd reset. these can be individually changed after power up through the selection register shown. table 111. multiplexed pins power up defaults table 112 shows the pin defaults that are determined by rom_kbcs# at the trailing edge of pwrgd reset. table 112. multiplexed pins determined by rom_kbcs# pin name alternate gpio pin selection register smbusc gpio0 pm00 +c0h smbusd gpio1 pm00 +c1h therm# pmirq0 gpio2 pm00 +c2h slpbtn# pmirq1 gpio3 pm00 +c3h (this pin can also be specified to be extirq8#) suspend# gpio4 pm00 +c4h cpusleep# pnpcs0# gpio5 pm00 +c5h cpustop# pnpcs1# gpio6 pm00 +c6h pcistop# pnpirq0 gpio7 pm00 +c7h cache_zz pnpirq1 gpio8 pm00 +c8h dcstop# pnpirq2 gpio9 pm00 +c9h flagwr pnpdrq gpio10 pm00 +cah flagrd# pnpdak# gpio11 pm00 +cbh extsmi# bmreq# gpio12 pm00 +cch keylock dbrdy gpio13 pm00 +cdh ri# gpio14 pm00 +ceh c32khz gpio15 pm00 +cfh intirq8# sqwave gpio16 pm00 +d0h serirq msirq gpio17 pm00 +d1h irq12 smbalert# function 3 offset 46 bits[10:9] (this can also be a second usb over-current indicator, usboc1#) pin name alternate selection register kbck ka20g function 3 offset 48 bit[intkbc] kbdt kbrc# function 3 offset 48 bit[intkbc] msck ekirq1 function 3 offset 48 bit[intkbc] msdt ekirq12 function 3 offset 48 bit[intkbc]
chapter 10 pin designations 337 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information table 113 show the pins that are multiplexed between the control signals for the second processor and AMD-756 peripheral bus controller internal interrupts. at power up, these signals all default to the processor interrupt signals. table 113. multiplexed pins selected by interrupt sources pin name alternate selection register picd1# pitirq function 0 offset 49 bit[rvlint] picd0# kbcirq function 0 offset 49 bit[rvlint] wsc# sciirq function 0 offset 49 bit[rvlint] picclk usbirq function 0 offset 49 bit[rvlint]
338 pin designations chapter 10 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
chapter 11 package specifications 339 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information 11 package specifications the AMD-756 peripheral bus controller comes in a 272-ball plastic ball grid array (pbga). the dimensions and thermal specifications are shown below. ja <= 25 o c/w jc = junction to case thermal resistance (not available) ca = case to ambient thermal resistance (not available) table 114. 272-pin pbga package preliminary specification symbol millimeters inches notes min typ max min typ max a 26.80 27.00 27.20 1.06 1.063 1.07 b 24.13 0.95 c 24.00 0.945 d 24.00 0.945 e 2.20 2.33 2.46 0.087 0.092 0.097 f 1.17 0.046 g 0.51 0.56 0.61 0.020 0.022 0.024 h 0.50 0.60 0.70 0.020 0.024 0.028 m 1.27 0,05
340 package specifications chapter 11 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information figure 54. 272 - pin pbga package preliminary specification a a c d m h a b c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d e f g h k l m n p r t u v w j y a b
chapter 11 package specifications 341 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information figure 55. 272 - pin pbga package preliminary specification, continued e f h g a a c d
342 package specifications chapter 11 AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information
index i-1 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information a a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 ad bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 , 85 , 96 address generation, dma . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 aen . . . . . . . . . . . . . . . . 29 , 79 , 308 , 310 , 315 , 317 , 319 , 328 agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 apiccs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 35 apm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 , 223 arbiter, ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 arbitration, pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 b back-to-back cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 bale . . . . . . . . . . . . . . . . . . . . 29 , 72 , 79 , 306 , 308 , 310 , 328 base class code (function 1) . . . . . . . . . . . . . . .263 , 278 ? 281 base class code, function 3 . . . . . . . . . . . . . . . . . . . . 225 , 272 bclk . . . . . . . . . . . . . . . . . . 29 , 69 , 89 , 91 , 98 , 105 , 305 , 328 block diagram, amd-645 peripheral bus controller . . . . . 14 bus arbitration, pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 bus master ide register i/o location . . . . . . . . . . . . . . . . . 83 bus master initiated cycles, isa . . . . . . . . . . . . . . . . . . . . . 80 bus master reload (bms_rld) . . . . . . . . . . . . . . . . . . . . . 245 bus master status (bm_sts) . . . . . . . . . . . . . . . . . . . . . . . . 243 bus master, function 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 c c/be[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 74 , 302 channel mapping registers, dma . . . . . . . . . . . . . . . . . . . . 98 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 cmos/rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 command register, function 3 . . . . . . . . . . . . . . . . . . 224 , 270 configuration read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 configuration registers agp virtual address space . 238 ? 241 , 260 , 263 , 278 ? 281 , 285 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 base address register 1. . . . . . . . . . . . . . . . . . . . . . . . . . 272 base class code, function 3 . . . . . . . . . . . . . . . . . . 225 , 272 command register, function 3 . . . . . . . . . . . . . . . . 224 , 270 device id, function 3 . . . . . . . . . . . . . . . . . . . . . . . . 224 , 270 general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 general purpose sci enable . . . . . . . . . . . . . . . . . . . . . . 249 general purpose smi enable . . . . 250 , 252 ? 253 , 255 ? 256 general purpose status (gp_sts) . . . . . . . . . . . . . . . . . 248 gpi port input value (gpi_val) .274 , 276 ? 278 , 280 ? 281 , 283 gpio direction control (gpio_dir) . . . . . . . . . . . . . . . 260 gpio port output value (gpio_val) . 268 ? 269 , 275 ? 276 , 285 gpo port output value (gpo_val). . . . . . . . . . . . 265 ? 269 header type, function 3 . . . . . . . . . . . . . . . . .225 , 272 ? 273 i/o register base address . . . . . . . . . . . . . . . . . . . . . . . . 230 latency timer, function 3 . . . . . . . . . . . . . . . . . . . . 225 , 272 master interrupt controller . . . . . . . . . . . . . . . . . . . . . . 194 power management control . . . . . . . . . . . . . . . . . . . . . . 245 power management enable . . . . . . . . . . . . . . . . . . . . . . . 244 power management status. . . . . . . . . . . . . . . . . . . . 239 , 243 power management timer . . . . . . . . . . . . . . . . . . . . . . . 246 primary activity detect enable . . . . . . . . . . . 257 ? 258 , 282 primary activity detect status . . . . . . . . . . . . . . . . . . . 257 primary interrupt channel . . . . . . . . . . . . . . . . . . . . . . . 227 processor control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 processor level 3 (p_lvl3) . . . . . . . . . . . . . . . . . . . . . . 248 programming interface, function 3 . . . . . . . . . . . . 224 , 271 revision id, function 3. . . . . . . . . . . . . . . . . . . . . . 224 , 271 sci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 226 , 231 ? 233 secondary channel prd table address . . . . . . . . . . . . 223 secondary interrupt channel. . . . . . . . . . . . . . . . . . . . . 228 slave interrupt controller . . . . . . . . . . . . . . . . . . . . . . . 194 smi command (smi_cmd) . . . . . . . . . . . . . . . . . . . . . . 256 status function 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 status, function 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 sub class code, function 3 . . . . . . . . . . . . . . . . . . 225 , 272 vendor id, function 3 . . . . . . . . . . . . . . . . . . . . . . . 224 , 270 cpu interface apiccs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 35 cpurst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 329 ferr#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 329 ignne#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 329 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 162 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 247 ? 248 , 329 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 30 , 159 signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ? 21 , 329 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 247 ? 248 , 329 cpurst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 329 d da[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 321 dack#. . . . . . . . . . . . . . . . . 78 , 93 , 98 ? 99 , 314 ? 315 , 317 , 319 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 dd[15:0] . . . . . . . . . . . . . . . . . . . . . . . 39 ? 40 , 42 ? 45 , 321 , 323 ddacka# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ddackb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ddmardya#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 328 ddmardyb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ddrqa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ? 41 , 328 ddrqb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ? 42 , 328 decoding, subtractive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 device id, function 3 . . . . . . . . . . . . . . . . . . . . . . . . . 224 , 270 devsel# . . . . . . . . . 9 ? 10 , 23 , 28 , 75 , 84 ? 87 , 271 , 302 , 328 diora#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diorb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diowa# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diowb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 direct memory access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 distributed dma control . . . . . . . . . . . . . . . . . . . . . . . . . . 212 distributed dma support. . . . . . . . . . . . . . . . . . . . . . . . . . 100 dma address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 channel mapping registers . . . . . . . . . . . . . . . . . . . . . . . 98 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 controller i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . 192 controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 dack#. . . . . . . . . . . . . . . 78 , 93 , 98 ? 99 , 314 ? 315 , 317 , 319
i-2 index AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information -initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 slave & master controllers . . . . . . . . . . . . . . . . . . . . . . . . 92 software commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 support, distributed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 type f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 drdya#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 drdyb#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 driven. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dstrobea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 dstrobeb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 dual address line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 e ed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 eide controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 eide interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 extended timer value (etm_val) . . . . . . . . . . . . . . . . . . 246 external cascading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 extsmi[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 f fast ide/eide interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 ferr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 329 flash memory support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 floated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 frame# . . . . . . . . . . . . . . . . .22 ? 24 , 66 ? 67 , 75 , 81 , 302 , 328 function 0 registers (pci-isa bridge). . . . . . . . . . . . . . . . 202 function 1 pci configuration space header. . . . . . . . . . . 213 function 1 registers (enhanced ide controller) . . . . . . . 212 function 1 registers, initiation. . . . . . . . . . . . . . . . . . . . . . 164 function 2 registers, initiation. . . . . . . . . . . . . . . . . . . . . . 171 function 3 pci configuration space header. . . . . . . 224 , 270 function 3 registers (power management) . . . . . . . . 223 , 270 function 3 registers, initiation. . . . . . . . . . . . . . . . . . . . . . 166 g general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 general purpose status (gp_sts) . . . . . . . . . . . . . . . . . . . 248 global release (gbl_rls) . . . . . . . . . . . . . . . . . . . . . . . . . 245 global status (gbl_sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 gpi port input value (gpi_val)274 , 276 ? 278 , 280 ? 281 , 283 gpi_re# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 gpio bus direction control (gpio_dir) . . . . . . . . . . . . . . . . . . . . 260 gpi_re# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 port output value (gpio_val) . . 268 ? 269 , 275 ? 276 , 285 gpo port output value (gpo_val). . . . . . . . . . . . . . 265 ? 269 h hdmardya# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hdmardyb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 header type, function 3 . . . . . . . . . . . . . . . . . . .225 , 272 ? 273 hstrobea# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 i i/o and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 location (off-chip), isa bus . . . . . . . . . . . . . . . . . . . . . . 83 location (on-chip), isa bus. . . . . . . . . . . . . . . . . . . . . . . 83 location, bus master ide register . . . . . . . . . . . . . . . . . 83 location, ide bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 on-chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 register base address. . . . . . . . . . . . . . . . . . . . . . . . . . . 230 registers, legacy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 sa bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 space registers, power management . . . . . . . . . . . . . . 169 space, function 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 ide arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus i/o location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 configuration registers . . . . . . . . . . . . . . . . . . . . . 106 , 218 da[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 321 dd[15:0] . . . . . . . . . . . . . . . . . . . . . 39 ? 40 , 42 ? 45 , 321 , 323 ddacka# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ddackb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ddmardya#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 328 ddmardyb#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ddrqa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ? 41 , 328 ddrqb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ? 42 , 328 diora#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diorb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diowa# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diowb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 drdya# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 drdyb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 drive registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 dstrobea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 dstrobeb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hdmardya#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hdmardyb#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 hstrobea# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 soe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 , 323 stopa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 stopb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 idsel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 75 , 176 , 328 ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 329 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 162 interface timing dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 eide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 isa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 pci. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 ultra dma-33 ide bus . . . . . . . . . . . . . . . . . . . . . . . . . . 325 internal real-time clock irq8# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 rtc enable (rtc_en) . . . . . . . . . . . . . . . . . . . . . . . . . . 244 rtc status (rtc_sts) . . . . . . . . . . . . . . . . . . . . . . . . . . 243 rtcx1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 rtcx2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 , 245 interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 247 ? 248 , 329 invalidate, memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 iochck# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 328
index i-3 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information iochrdy9 , 31 , 64 , 69 , 77 , 79 , 81 , 86 , 98 ? 99 , 306 , 308 , 310 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 , 315 , 317 , 328 iocs16# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 308 , 310 , 328 ior# . . . . . . . . . . . 12 , 32 , 79 , 81 , 85 , 308 , 310 , 317 , 319 , 328 iow#. . . . . . . . . . . 12 , 32 , 79 , 81 , 85 , 308 , 310 , 315 , 319 , 328 irdy#. . . . . . . . . . . . . 10 , 24 ? 25 , 66 ? 67 , 75 , 78 , 81 , 302 , 328 irq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 191 , 227 irq12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 , 329 irq8# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 isa bus aen . . . . . . . . . . . . . . 29 , 79 , 308 , 310 , 315 , 317 , 319 , 328 bale . . . . . . . . . . . . . . . . . . 29 , 72 , 79 , 306 , 308 , 310 , 328 bclk . . . . . . . . . . . . . . . . 29 , 69 , 89 , 91 , 98 , 105 , 305 , 328 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 i/o location (off-chip) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 i/o location (on-chip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 -initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 iochck# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 328 iochrdy . 9 , 31 , 64 , 69 , 77 , 79 , 81 , 86 , 98 ? 99 , 306 , 308 , 310 , . . . . . . . . . . . . . . . . . . . . . . . . . 312 , 315 , 317 , 328 iocs16# . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 308 , 310 , 328 ior# . . . . . . . . . 12 , 32 , 79 , 81 , 85 , 308 , 310 , 317 , 319 , 328 iow# . . . . . . . . 12 , 32 , 79 , 81 , 85 , 308 , 310 , 315 , 319 , 328 la[23:17] . . . . . . . . . . . . . . . . . . . 29 , 33 , 306 , 312 , 315 , 317 master initiated cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 master# . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 , 80 , 99 , 328 memcs16# . . . . . . . . . . . . . . . . . . . . . 34 , 68 , 306 , 312 , 328 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 memr# . . . . . . 34 , 68 , 72 , 79 , 81 , 105 , 306 , 312 , 315 , 328 memw# . . . . . . . . . . . . . 34 , 68 , 79 , 81 , 306 , 312 , 317 , 328 off-board memory location . . . . . . . . . . . . . . . . . . . . . . . 84 osc. . . . . . . . . . . . . . . . . . . . . .29 , 35 , 88 ? 89 , 105 , 300 , 328 refresh cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 refresh# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 105 , 328 rstdrv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 328 sa16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 sbhe# . . . . . . . . . . . . . . . . 29 , 36 , 66 , 74 , 95 ? 96 , 306 , 328 sd[15:0] . . . . . . . . . . . 36 , 84 , 306 , 308 , 310 , 312 , 315 , 317 sd[15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 310 , 312 , 319 sd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 smemr# . . . . . . . . . . . . . . . . . . . . . . . . 36 , 68 , 72 , 306 , 315 smemw# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 68 , 317 tc . . . . . . . . . . . . . . 37 , 68 ? 69 , 79 , 103 , 315 , 317 , 319 , 328 k kbck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 kbcs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 kbdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 kbrc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 keyboard a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 controller command codes. . . . . . . . . . . . . . . . . . . . . . . 189 irq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 191 , 227 irq12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 , 329 kbck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 kbdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 kbrc#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 keylock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 msck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ? 60 msdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 329 signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 keylock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 l la[23:17] . . . . . . . . . . . . . . . . . . . . 29 , 33 , 306 , 312 , 315 , 317 latency timer, function 3 . . . . . . . . . . . . . . . . . . . . . 225 , 272 legacy i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . 158 , 187 lvl3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 m mapping registers, dma channel. . . . . . . . . . . . . . . . . . . . 98 mapping, i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 mapping, i/o and memory . . . . . . . . . . . . . . . . . . . . . . . . . . 83 mapping, memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mapping, system rom memory. . . . . . . . . . . . . . . . . . . . . . 86 master clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 master ide register i/o location, bus . . . . . . . . . . . . . . . . 83 master interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . 194 master mode, pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 master# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 , 80 , 99 , 328 memcs16# . . . . . . . . . . . . . . . . . . . . . . . 34 , 68 , 306 , 312 , 328 memory isa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mapping, i/o and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 mapping, system rom . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 read line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 read multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 space, function 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 memr# . . . . . . . . 34 , 68 , 72 , 79 , 81 , 105 , 306 , 312 , 315 , 328 memw# . . . . . . . . . . . . . . . 34 , 68 , 79 , 81 , 306 , 312 , 317 , 328 middle address bit latches . . . . . . . . . . . . . . . . . . . . . . . . . 93 mirq0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 mirq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ? 48 mirq2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 miscellaneous i/o functions. . . . . . . . . . . . . . . . . . . . . . . . 201 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 msck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ? 60 msdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 329 n negated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 30 , 159 o on-chip i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 onnow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 osc . . . . . . . . . . . . . . . . . . . . . . . 29 , 35 , 88 ? 89 , 105 , 300 , 328 p page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
i-4 index AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information par. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 328 pausing a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 pc97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pci ad bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 , 85 , 96 c/be[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 74 , 302 devsel#. . . . . . . . . . . . 9 ? 10 , 23 , 28 , 75 , 84 ? 87 , 302 , 328 frame# . . . . . . . . . . . . . . .22 ? 24 , 66 ? 67 , 75 , 81 , 302 , 328 idsel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 75 , 176 , 328 irdy#. . . . . . . . . . . 10 , 24 ? 25 , 66 ? 67 , 75 , 78 , 81 , 302 , 328 par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 328 pcirst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 328 pclk 23 , 25 ? 26 , 29 , 88 ? 89 , 297 , 299 ? 301 , 303 ? 305 , 321 , 323 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 , 328 pgnt# . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 83 , 91 , 302 , 328 preq# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 , 83 , 302 , 328 serr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 27 , 328 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 , 67 , 302 , 328 trdy# . . . . . . . . . . . . . . . . . . . 28 , 64 , 67 , 75 , 81 , 302 , 328 pci bus bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 bus features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bus-initiated accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 devsel#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 function 1 registers ? ide control . . . . . . . . . . . . . . . . 164 function 2 registers ? usb controller. . . . . . . . . . . . . . 171 function 3 registers ? power management . . . . . . . . . . 166 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 mechanism #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 pci-to-isa bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 slave dma configuration registers . . . . . . . . . . . . . . . . 105 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 pcirst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 328 pclk . . 23 , 25 ? 26 , 29 , 88 ? 89 , 297 , 299 ? 301 , 303 ? 305 , 321 , 323 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 , 328 pclk switching characteristics . . . . . . . . . . . . . . . . . 300 , 303 pgnt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 83 , 91 , 302 , 328 pin designation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 plug-n-play control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 mirq0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 mirq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ? 48 mirq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 power & ground agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 vdd . . . . . . . . . . . . . . . . . . . . . . . . . . 62 , 245 , 293 , 296 , 329 vdd3 . . . . . . . . . . . . . . . . . . . . . 62 , 293 ? 294 , 296 ? 297 , 329 vdd-5sb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 vdd-pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 power button enable (pb_en) . . . . . . . . . . . . . . . . . . . . . . 244 power button override status (pbor_sts) . . . . . . . . . . . 243 power button status (pb_sts) . . . . . . . . . . . . . . . . . . . . . . 243 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 power management acpi timer count select . . . . . . . . . . . . . . . . . . . . . . . . . 225 acpi timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 225 configuration space registers . . . . . . . . . . . . . . . . . . . . 166 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 enable for acpi i/o base . . . . . . . . . . . . . . . . . . . . . . . . 225 extsmi[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 extsmi1# toggle status (ext1_sts) . . . . . . . . . . . . . 248 general purpose sci enable . . . . . . . . . . . . . . . . . . . . . 249 general purpose smi enable . . . . . 250 , 252 ? 253 , 255 ? 256 i/o register base address. . . . . . . . . . . . . . . . . . . . . . . . 228 i/o space registers . . . . . . . . . . . . . . . . . . . . . . . . . 169 , 242 pwrbtn#. . . . . . . . . . . . . . . . . . . . . . . . . . 52 , 243 , 247 ? 248 pwrgd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 pwron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 ri# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 sci enable (sci_en). . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 sci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 226 , 231 ? 233 sci interrupt assignment. . . . . . . . . . . . . . . . . . . . . . . . 226 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 , 243 subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 timer enable (tmr_en) . . . . . . . . . . . . . . . . . . . . . . . . 244 power plane management. . . . . . . . . . . . . . . . . . . . . . 112 , 117 power-up straps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 prd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 ? 223 preq#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 , 83 , 302 , 328 primary activity detect enable . . . . . . . . . . . . . 257 ? 258 , 282 primary activity detect status . . . . . . . . . . . . . . . . . . . . . 257 primary interrupt channel . . . . . . . . . . . . . . . . . . . . . . . . . 227 processor control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 processor level 3 (p_lvl3) . . . . . . . . . . . . . . . . . . . . . . . . 248 programming interface, function 3 . . . . . . . . . . . . . . 224 , 271 pwrbtn#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 , 243 , 247 ? 248 pwrgd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 pwron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 r ratings, absolute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 read/write, configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 75 read/write, memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ready control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 refresh cycle types, isa bus. . . . . . . . . . . . . . . . . . . . . . . 105 refresh# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 105 , 328 request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 revision id, function 3. . . . . . . . . . . . . . . . . . . . . . . . 224 , 271 ri# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 rom memory mapping, system. . . . . . . . . . . . . . . . . . . . . . 86 romcs# . . . . . . . . . . . . . . . . . . . . . . . . . . .84 , 86 ? 87 , 162 , 205 rstdrv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 328 rtc enable (rtc_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 rtc status (rtc_sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 rtcx1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 rtcx2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 s sa bus i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 sa16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 sbhe# . . . . . . . . . . . . . . . . . . . 29 , 36 , 66 , 74 , 95 ? 96 , 306 , 328 sd[15:0] . . . . . . . . . . . . . 36 , 84 , 306 , 308 , 310 , 312 , 315 , 317
index i-5 22548b/0 ? august 1999 AMD-756 ? peripheral bus controller data sheet preliminary information sd[15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 310 , 312 , 319 sd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 secondary channel prd table address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 secondary interrupt channel . . . . . . . . . . . . . . . . . . . . . . . 228 serr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 27 , 328 signal terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signals a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 ad bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 , 85 , 96 aen . . . . . . . . . . . . . . 29 , 79 , 308 , 310 , 315 , 317 , 319 , 328 agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 apiccs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 35 avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 bale . . . . . . . . . . . . . . . . . . 29 , 72 , 79 , 306 , 308 , 310 , 328 bclk . . . . . . . . . . . . . . . . 29 , 69 , 89 , 91 , 98 , 105 , 305 , 328 c/be[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 74 , 302 cpurst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 329 da[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 321 dack# . . . . . . . . . . . . . . .78 , 93 , 98 ? 99 , 314 ? 315 , 317 , 319 dd[15:0]. . . . . . . . . . . . . . . . . . . . . . 39 ? 40 , 42 ? 45 , 321 , 323 ddacka# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ddackb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ddmardya# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 328 ddmardyb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ddrqa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 ? 41 , 328 ddrqb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 ? 42 , 328 devsel#. . . . . . . . 9 ? 10 , 23 , 28 , 75 , 84 ? 87 , 271 , 302 , 328 diora# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diorb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diowa# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 , 328 diowb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 drdya#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 drdyb#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 328 dstrobea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 dstrobeb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 extsmi[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ferr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 329 frame# . . . . . . . . . . . . . . .22 ? 24 , 66 ? 67 , 75 , 81 , 302 , 328 gpi_re# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 hdmardya# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hdmardyb# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 hstrobea# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 idsel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 75 , 176 , 328 ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 329 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 162 intr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 247 ? 248 , 329 iochck# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 328 iochrdy . 9 , 31 , 64 , 69 , 77 , 79 , 81 , 86 , 98 ? 99 , 306 , 308 , 310 , . . . . . . . . . . . . . . . . . . . . . . . . . 312 , 315 , 317 , 328 iocs16# . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 308 , 310 , 328 ior# . . . . . . . . . 12 , 32 , 79 , 81 , 85 , 308 , 310 , 317 , 319 , 328 iow# . . . . . . . . 12 , 32 , 79 , 81 , 85 , 308 , 310 , 315 , 319 , 328 irdy#. . . . . . . . . . . 10 , 24 ? 25 , 66 ? 67 , 75 , 78 , 81 , 302 , 328 irq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 191 , 227 irq12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 , 329 irq8# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 kbck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 kbcs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 kbdt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 kbrc#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 , 329 keylock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 la[23:17] . . . . . . . . . . . . . . . . . . 29 , 33 , 306 , 312 , 315 , 317 master# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 , 80 , 99 , 328 memcs16# . . . . . . . . . . . . . . . . . . . . . 34 , 68 , 306 , 312 , 328 memr# . . . . . . 34 , 68 , 72 , 79 , 81 , 105 , 306 , 312 , 315 , 328 memw# . . . . . . . . . . . . . 34 , 68 , 79 , 81 , 306 , 312 , 317 , 328 mirq0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 mirq1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ? 48 mirq2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 msck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ? 60 msdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 329 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 30 , 159 osc . . . . . . . . . . . . . . . . . . . . . 29 , 35 , 88 ? 89 , 105 , 300 , 328 par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 328 pcirst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 328 pclk .23 , 25 ? 26 , 29 , 88 ? 89 , 297 , 299 ? 301 , 303 ? 305 , 321 , 323 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 , 328 pgnt#. . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 83 , 91 , 302 , 328 preq#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 , 83 , 302 , 328 pwrbtn#. . . . . . . . . . . . . . . . . . . . . . . . . . 52 , 243 , 247 ? 248 pwrgd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 pwron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 refresh#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 105 , 328 ri# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 romcs# . . . . . . . . . . . . . . . . . . . . . . . . .84 , 86 ? 87 , 162 , 205 rstdrv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 328 rtcx1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 rtcx2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 sa16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 sbhe# . . . . . . . . . . . . . . . . . 29 , 36 , 66 , 74 , 95 ? 96 , 306 , 328 sd[15:0] . . . . . . . . . . . 36 , 84 , 306 , 308 , 310 , 312 , 315 , 317 sd[15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 310 , 312 , 319 sd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 serr#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 , 27 , 328 smemr#. . . . . . . . . . . . . . . . . . . . . . . . 36 , 68 , 72 , 306 , 315 smemw# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 68 , 317 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ? 21 , 329 soe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 , 323 spkr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 stop# . . . . . . . . . . . . . . . . . . . . . . . . . 28 , 67 , 271 , 302 , 328 stopa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 stopb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 247 ? 248 , 329 tc . . . . . . . . . . . . . .37 , 68 ? 69 , 79 , 103 , 315 , 317 , 319 , 328 trdy#. . . . . . . . . . . . . . . . . . . . 28 , 64 , 67 , 75 , 81 , 302 , 328 usbclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 , 303 , 329 usbdata0 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 usbdata0+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 , 329 vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 , 245 vdd. . . . . . . . . . . . . . . . . . . . . . . . . . 62 , 245 , 293 , 296 , 329 vdd3. . . . . . . . . . . . . . . . . . . . . 62 , 293 ? 294 , 296 ? 297 , 329 vdd-5sb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 xd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 xdir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 single-channel mask register . . . . . . . . . . . . . . . . . . . . . . 103 slave & master dma controllers . . . . . . . . .ports c0h ? dfh92 slave dma channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 slave interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . 194
i-6 index AMD-756 ? peripheral bus controller data sheet 22548b/0 ? august 1999 preliminary information slave mode, pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 sleep enable (slp_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 sleep type (slp_typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 smemr# . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 68 , 72 , 306 , 315 smemw# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 68 , 317 smi command (smi_cmd) . . . . . . . . . . . . . . . . . . . . . . . . . 256 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 ? 21 , 329 smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 soe#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 , 323 software commands, dma . . . . . . . . . . . . . . . . . . . . . . . . . 103 special cycle monitoring, function 0 . . . . . . . . . . . . . . . . 270 spkr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 state machine, dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 status, function 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 , 67 , 271 , 302 , 328 stopa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 stopb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 247 ? 248 , 329 sub class code, function 3 . . . . . . . . . . . . . . . . . . . . . 225 , 272 subtractive decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 switching characteristics, pclk . . . . . . . . . . . . . . . . 300 , 303 system rom memory mapping. . . . . . . . . . . . . . . . . . . . . . . 86 t table, pin designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 tc . . . . . . . . . . . . . . . . 37 , 68 ? 69 , 79 , 103 , 315 , 317 , 319 , 328 terminology, signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 throttling duty cycle (tht_dty) . . . . . . . . . . . . . . . . . . . 247 timer carry status (tmr_sts) . . . . . . . . . . . . . . . . . . . . . 243 timer value (tmr_val) . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 timer/counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 timing, dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 timing, isa interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 timing, pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 timing, ultra dma-33 ide bus interface . . . . . . . . . . . . . 325 trdy# . . . . . . . . . . . . . . . . . . . . . 28 , 64 , 67 , 75 , 81 , 302 , 328 type f dma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 u ultra dma ide bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . 325 ultra dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ultra dma-33 ide bus interface timing . . . . . . . . . . . . . 325 universal serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 usb signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 usbclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 , 303 , 329 usbdata0 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 usbdata0+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 , 329 usbclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 , 303 , 329 usbdata0 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 usbdata0+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 , 329 v vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 , 245 vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 , 245 , 293 , 296 , 329 vdd3. . . . . . . . . . . . . . . . . . . . . . . 62 , 293 ? 294 , 296 ? 297 , 329 vdd-5sb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 vdd-pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 vendor id, function 3 . . . . . . . . . . . . . . . . . . . . . . . . . 224 , 270 w wakeup status (wak_sts) . . . . . . . . . . . . . . . . . . . . . . . . 243 write burst, pausing a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 x x-bus kbcs# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 romcs# . . . . . . . . . . . . . . . . . . . . . . . . .84 , 86 ? 87 , 162 , 205 xd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 xdir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 xd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 xdir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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